<title>Generalized matrix product and its relation to parallel architecture communication</title>

Recent events in the high-performance computing industry have concerned scientists and the general public regarding a crisis or a lack of leadership in the field. That concern is understandable considering the industry's history from 1993 to 1996. Cray Research, the historic leader in supercomputing technology, was unable to survive financially as an independent company and was acquired by Silicon Graphics. Two ambitious new companies that introduced new technologies in the late 1980s and early 1990s—Thinking Machines and Kendall Square Research—were commercial failures and went out of business. And Intel, which introduced its Paragon supercomputer in 1994, discontinued production only two years later.During the same time frame, scientists who had finished the laborious task of writing scientific codes to run on vector parallel supercomputers learned that those codes would have to be rewritten if they were to run on the next-generation, highly parallel architecture. Scientists who are not yet involved in high-performance computing are understandably hesitant about committing their time and energy to such an apparently unstable enterprise.However, beneath the commercial chaos of the last several years, a technological revolution has been occurring. The good news is that the revolution is over, leading to five to ten years of predictable stability, steady improvements in system performance, and increased productivity for scientific applications. It is time for scientists who were sitting on the fence to jump in and reap the benefits of the new technology.

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A generalized matrix-fracture flow transfer model for fractured porous media

Journal of Porous Media ◽

10.1615/jpormedia.2021034619 ◽

2021 ◽

Author(s):

Zhechao wang ◽

Jiafan guo ◽

Zhejun pan ◽

Liping qiao ◽

Jie liu ◽

...

Keyword(s):

Porous Media ◽

Fractured Porous Media ◽

Transfer Model ◽

Fracture Flow ◽

Matrix Fracture ◽

Generalized Matrix ◽

Flow Transfer

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Iterative criterion of the descriptor system asymptotic steadiness

Automation. Modern Techologies ◽

10.36652/0869-4931-2020-74-5-213-219 ◽

2020 ◽

Keyword(s):

Iterative Algorithm ◽

Search Algorithm ◽

Descriptor System ◽

Matrix Sign Function ◽

Sign Function ◽

Generalized Matrix ◽

Criterion Matrix

An iterative criterion for the asymptotic steadiness of a linear descriptor system is considered. The criterion is based on an iterative algorithm for computing a generalized matrix sign-function. As an example, the problem of analyzing the asymptotic steadiness of a large descriptor system is given. Keywords linear descriptor system; steadiness criterion; matrix sign-function; search algorithm

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PROTEUS: A High-Performance Parallel-Architecture Simulator

10.21236/ada241343 ◽

1991 ◽

Cited By ~ 99

Author(s):

Eric A. Brewer ◽

Chrysanthos N. Dellarocas ◽

Adrian Colbrook ◽

William E. Weihl

Keyword(s):

High Performance ◽

Parallel Architecture

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Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽

10.3390/electronics10091106 ◽

2021 ◽

Vol 10 (9) ◽

pp. 1106

Author(s):

Vladimir L. Petrović ◽

Dragomir M. El Mezeni ◽

Andreja Radošević

Keyword(s):

Channel Coding ◽

Parallel Architecture ◽

Ldpc Codes ◽

Parity Check ◽

Case Scenario ◽

New Radio ◽

Physical Channel ◽

Computationally Intensive ◽

Hardware Processing ◽

Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

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