Design of a polarization insensitive mode-size converter worked at 800 nm wavelength with simple CMOS process

2021 ◽  
Author(s):  
Heming Hu ◽  
Juan Hu ◽  
Shuxiao Wang ◽  
Miaomiao Gu ◽  
Xindan Zhang ◽  
...  
Keyword(s):  
Cmos Process ◽  
Polarization Insensitive ◽  
Mode Size

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  
Cmos Process ◽  
Flash Adc

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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