A 32×32 SPAD array based readout integrated circuit for LiDAR applications

2020 ◽  
Author(s):  
Jing Cao ◽  
Xiaoyan Hu ◽  
Lijun Yang ◽  
Bin Li
Keyword(s):  
Integrated Circuit ◽  
Readout Integrated Circuit

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

Advanced readout integrated circuit signal processing

2006 ◽  
Author(s):  
Allen Hairston ◽  
James Stobie ◽  
Rosanne Tinkler
Keyword(s):  
Signal Processing ◽  
Integrated Circuit ◽  
Readout Integrated Circuit

Development of a 64 × 64 CdZnTe array and associated readout integrated circuit for use in nuclear medicine

1997 ◽  
Vol 26 (6) ◽  
pp. 765-772 ◽  
Author(s):  
H. B. Barber ◽  
H. H. Barrett ◽  
F. L. Augustine ◽  
W. J. Hamilton ◽  
B. A. Apotovsky ◽  
...  
Keyword(s):  
Nuclear Medicine ◽  
Integrated Circuit ◽  
Readout Integrated Circuit

scholarly journals A New CDS Structure for High Density FPA with Low Power

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi
Keyword(s):  
Integrated Circuit ◽  
Dominant Role ◽  
Noise Analysis ◽  
Calculation Model ◽  
High Density ◽  
Integration Time ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Long Wave ◽  
Layout Area

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

Pixel readout IC for CdTe detectors operating in single photon counting mode with interpixel communication

2022 ◽  
Vol 17 (01) ◽  
pp. C01036
Author(s):  
P. Grybos ◽  
R. Kleczek ◽  
P. Kmon ◽  
A. Krzyzanowska ◽  
P. Otfinowski ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Single Photon ◽  
Photon Counting ◽  
Recognition Algorithm ◽  
Total Charge ◽  
Readout Integrated Circuit ◽  
Single Photon Counting ◽  
X Ray ◽  
Pixel Detectors ◽  
Photon Counting Mode

Abstract This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).

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