Anomaly detection of solder joint on print circuit board by using Adversarial Autoencoder

2019 ◽  
Author(s):  
Keisuke Goto ◽  
Kunihito Kato ◽  
Shunsuke Nakatsuka ◽  
Takaho Saito ◽  
Hiroaki Aizawa
Keyword(s):  
Solder Joint ◽  
Anomaly Detection ◽  
Print Circuit Board ◽  
Circuit Board

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Effect of intermetallic compound layer thickness on the shear strength of 1206 chip resistor solder joint

2015 ◽  
Vol 27 (1) ◽  
pp. 52-58 ◽  
Author(s):  
Peter K. Bernasko ◽  
Sabuj Mallik ◽  
G. Takyi
Keyword(s):  
Shear Strength ◽  
Intermetallic Compound ◽  
Solder Joint ◽  
Layer Thickness ◽  
Solder Joints ◽  
Ageing Time ◽  
Circuit Board ◽  
Intermetallic Compound Layer ◽  
Content Type ◽  
Surface Mount

Purpose – The purpose of this paper is to study the effect of intermetallic compound (IMC) layer thickness on the shear strength of surface-mount component 1206 chip resistor solder joints. Design/methodology/approach – To evaluate the shear strength and IMC thickness of the 1206 chip resistor solder joints, the test vehicles were conventionally reflowed for 480 seconds at a peak temperature of 240°C at different isothermal ageing times of 100, 200 and 300 hours. A cross-sectional study was conducted on the reflowed and aged 1206 chip resistor solder joints. The shear strength of the solder joints aged at 100, 200 and 300 hours was measured using a shear tester (Dage-4000PXY bond tester). Findings – It was found that the growth of IMC layer thickness increases as the ageing time increases at a constant temperature of 175°C, which resulted in a reduction of solder joint strength due to its brittle nature. It was also found that the shear strength of the reflowed 1206 chip resistor solder joint was higher than the aged joints. Moreover, it was revealed that the shear strength of the 1206 resistor solder joints aged at 100, 200 and 300 hours was influenced by the ageing reaction times. The results also indicate that an increase in ageing time and temperature does not have much influence on the formation and growth of Kirkendall voids. Research limitations/implications – A proper correlation between shear strength and fracture mode is required. Practical implications – The IMC thickness can be used to predict the shear strength of the component/printed circuit board pad solder joint. Originality/value – The shear strength of the 1206 chip resistor solder joint is a function of ageing time and temperature (°C). Therefore, it is vital to consider the shear strength of the surface-mount chip component in high-temperature electronics.

Influence Of Solder Joint Shape On The Thermo-Mechanical Reliability Of CSP's

2004 ◽  
Vol 1 (2) ◽  
pp. 53-63 ◽  
Author(s):  
Co van Veen ◽  
Bart Vandevelde ◽  
Eric Beyne
Keyword(s):  
Solder Joint ◽  
Force Constant ◽  
Local Stress ◽  
Simulation Software ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Surface Evolver ◽  
Joint Shape ◽  
Profile Estimation ◽  
Analytical Expressions

Not only the stand-off height but also the shape of a solder joint has a strong influence on the joint reliability under temperature cycling. The shape determines the size of the local stress and strain concentrations. It is therefore very important to know well the joint shape after reflow. In a previous paper closed analytical expressions were derived for liquid bump shapes, as a function of pad size and bump height [1]. The bump deformation as a function of the chip weight could be derived from the force constant. In the present paper closed analytical expressions are derived for the force constant for liquid bumps having unequal spherical pad sizes. It turns out that the force constant for compression can be optimized as a function of the ratio of those pad sizes. The shape of the bump and especially the contact angle is of interest for modeling activities where geometrical effects do play a role. Furthermore from the variation in bumps heights on a chip an estimate can be made of the tilt of the chip after assembly. The solder profile estimation by the analytical expressions is validated by experimental results. Also a comparison with the solder profile estimation by the simulation software Surface Evolver is done. Both comparisons showed that the analytical estimation of the standoff height is very good as long as the gravitation energy contributed by the chip weight is less than 10% of the total energy. Finally, an example is shown where the analytical model and Surface Evolver are the geometrical input for a finite element model. The example considers a CSP assembled at both sides of the printed circuit board.

The Benefits of Flux-Coated Solder Preforms in a QFN Assembly Process

2015 ◽  
Vol 2015 (1) ◽  
pp. 000827-000832
Author(s):  
Brandon Judd ◽  
Maria Durham
Keyword(s):  
Mechanical Properties ◽  
Form Factor ◽  
Solder Joint ◽  
Circuit Board ◽  
Electrical Performance ◽  
Solder Paste ◽  
Assembly Process ◽  
Circuit Board Assembly ◽  
Difficult Challenge ◽  
Small Form Factor

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.

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