Line-edge roughness on fin-field-effect-transistor performance for below 10nm patterns

2019 ◽  
Author(s):  
So-Won Yoon ◽  
Sang-Kon Kim
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Line Edge Roughness ◽  
Edge Roughness ◽  
Effect Transistor

scholarly journals A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

Materials ◽  
2019 ◽  
Vol 12 (15) ◽  
pp. 2391 ◽  
Author(s):  
Natalia Seoane ◽  
Daniel Nagy ◽  
Guillermo Indalecio ◽  
Gabriel Espiñeira ◽  
Karol Kalna ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Three Dimensional ◽  
Gate Length ◽  
Line Edge Roughness ◽  
Voltage Standard ◽  
A Value ◽  
Edge Roughness ◽  
Effect Transistor ◽  
Study Performance ◽  
The Ideal

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 μA/μm, and an on-current (I ON) of 1770 μA/μm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55 . 5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

2010 ◽  
Vol E93-C (5) ◽  
pp. 540-545 ◽  
Author(s):  
Dong Seup LEE ◽  
Hong-Seon YANG ◽  
Kwon-Chil KANG ◽  
Joung-Eob LEE ◽  
Jung Han LEE ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

Biosensor Based on Ion-Sensitive Field-Effect Transistor Using Minimum Contact to Float-ing Gate

2019 ◽  
Vol 24 (4) ◽  
pp. 407-414
Author(s):  
Oksana V. Gubanova ◽  
◽  
Evgeniy V. Kuznetsov ◽  
Elena N. Rybachek ◽  
Alexander N. Saurov ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor
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