Method of glitch reduction in DAC with weight redundancy

Mapping Intimacies ◽

10.1117/12.2229045 ◽

2015 ◽

Cited By ~ 3

Author(s):

Olexiy D. Azarov ◽

Olexander G. Murashchenko ◽

Olexander I. Chernyak ◽

Andrzej Smolarz ◽

Gulzhan Kashaganova

Keyword(s):

Glitch Reduction

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Glitch reduction in second-generation SI circuits

Electronics Letters ◽

10.1049/el:19950437 ◽

1995 ◽

Vol 31 (8) ◽

pp. 597 ◽

Cited By ~ 5

Author(s):

O. Oliaei ◽

P. Loumeau

Keyword(s):

Second Generation ◽

Glitch Reduction

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Study of Gray code input DAC using MOSFETs for glitch reduction

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2016.7998849 ◽

2016 ◽

Cited By ~ 1

Author(s):

Gopal Adhikari ◽

Richen Jiang ◽

Haruo Kobayashi

Keyword(s):

Gray Code ◽

Glitch Reduction

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Review and Analysis of Glitch Reduction for Low Power VLSI Circuits

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2017.11201 ◽

2017 ◽

Vol V (XI) ◽

pp. 1386-1390 ◽

Cited By ~ 2

Author(s):

Somashekhar Malipatil

Keyword(s):

Low Power ◽

Vlsi Circuits ◽

Glitch Reduction

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A power optimization method considering glitch reduction by gate sizing

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280907 ◽

1998 ◽

Cited By ~ 11

Author(s):

Masanori Hashimoto ◽

Hidetoshi Onodera ◽

Keikichi Tamaru

Keyword(s):

Power Optimization ◽

Optimization Method ◽

Gate Sizing ◽

Glitch Reduction

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A practical gate resizing technique considering glitch reduction for low power design

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) ◽

10.1109/dac.1999.781358 ◽

2003 ◽

Cited By ~ 3

Author(s):

M. Hashimoto ◽

H. Onodera ◽

K. Tamaru

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Resizing ◽

Glitch Reduction

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A practical gate resizing technique considering glitch reduction for low power design

Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99 ◽

10.1145/309847.309977 ◽

1999 ◽

Cited By ~ 3

Author(s):

Masanori Hashimoto ◽

Hidetoshi Onodera ◽

Keikichi Tamaru

Keyword(s):

Low Power ◽

Low Power Design ◽

Gate Resizing ◽

Glitch Reduction

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A power optimization method considering glitch reduction by gate sizing

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708192 ◽

2002 ◽

Cited By ~ 2

Author(s):

M. Hashimoto ◽

H. Onodera ◽

K. Tamaru

Keyword(s):

Power Optimization ◽

Optimization Method ◽

Gate Sizing ◽

Glitch Reduction

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A current average control method for transient-glitch reduction in variable frequency DC-DC converters

2017 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2017.8050586 ◽

2017 ◽

Author(s):

Hsin-Shu Chen ◽

Jia-Nan Tai ◽

Yi-Jan Emery Chen ◽

Jau-Horng Chen

Keyword(s):

Control Method ◽

Variable Frequency ◽

Average Control ◽

Glitch Reduction ◽

A Current

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PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

2009 International Conference on Field-Programmable Technology ◽

10.1109/fpt.2009.5377666 ◽

2009 ◽

Cited By ~ 5

Author(s):

Xiao Dong ◽

Guy G.F. Lemieux

Keyword(s):

Clock Skew ◽

Clock Skew Scheduling ◽

Glitch Reduction

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Glitch reduction in digit-serial recursive filters using retiming

10.1109/icecs.2005.4633549 ◽

2005 ◽

Author(s):

Krister Landernas ◽

Johnny Holmberg ◽

Mark Vesterbacka

Keyword(s):

Recursive Filters ◽

Glitch Reduction

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