Error correction capability aware BCH implementation for NAND flash memories in Earth observation satellites

2015 ◽  
Author(s):  
M. Fatih Aydogdu ◽  
Yakup Murat Mert
Keyword(s):  
Error Correction ◽  
Earth Observation ◽  
Nand Flash ◽  
Flash Memories ◽  
Error Correction Capability ◽  
Earth Observation Satellites

Product Code Schemes for Error Correction in MLC NAND Flash Memories

2012 ◽  
Vol 20 (12) ◽  
pp. 2302-2314 ◽  
Author(s):  
Chengen Yang ◽  
Yunus Emre ◽  
Chaitali Chakrabarti
Keyword(s):  
Error Correction ◽  
Nand Flash ◽  
Flash Memories ◽  
Product Code

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

2022 ◽  
Vol 27 (1) ◽  
pp. 1-20
Author(s):  
Lanlan Cui ◽  
Fei Wu ◽  
Xiaojian Liu ◽  
Meng Zhang ◽  
Renzhi Xiao ◽  
...  
Keyword(s):  
Error Correction ◽  
Distribution Model ◽  
Quantization Scheme ◽  
Nand Flash ◽  
Soft Decision ◽  
Ldpc Decoding ◽  
Error Correction Capability ◽  
Soft Decision Decoding ◽  
Threshold Voltage Distribution ◽  
Hard Decision

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

2007 ◽  
Vol 1 (3) ◽  
pp. 241 ◽  
Author(s):  
F. Sun ◽  
S. Devarajan ◽  
K. Rose ◽  
T. Zhang
Keyword(s):  
Error Correction ◽  
Nand Flash ◽  
Flash Memories ◽  
On Chip
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