A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

2014 ◽  
Author(s):  
Min-Woong Seo ◽  
Keita Yasutomi ◽  
Keiichiro Kagawa ◽  
Shoji Kawahito
Keyword(s):  
Fill Factor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
High Fill Factor

A high fill-factor high-SNR CMOS image sensor for IR camera applications

2011 ◽  
Author(s):  
Varun Shenoy ◽  
Daniel McBride ◽  
Sungyong Jung ◽  
Hyejin Moon ◽  
Sang-Yeon Cho
Keyword(s):  
Fill Factor ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Ir Camera ◽  
High Fill Factor

High-fill-factor monolithic infrared image sensor

1991 ◽  
Author(s):  
Masafumi Kimata ◽  
Naoki Yutani ◽  
Hirofumi Yagi ◽  
Junji Nakanishi ◽  
Natsuro Tsubouchi ◽  
...  
Keyword(s):  
Fill Factor ◽  
Infrared Image ◽  
Image Sensor ◽  
High Fill Factor

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

1995 ◽  
Vol 42 (8) ◽  
pp. 1433-1440 ◽  
Author(s):  
S. Tohyama ◽  
K. Masubuchi ◽  
K. Konuma ◽  
H. Azuma ◽  
A. Tanabe ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Fill Factor ◽  
Image Sensor ◽  
Ccd Image Sensor ◽  
High Fill Factor ◽  
Progressive Scan ◽  
Ccd Image

High Fill Factor a-Si:H Sensor Arrays with Reduced Pixel Crosstalk

2008 ◽  
Vol 1066 ◽  
Author(s):  
Yuriy Vygranenko ◽  
A. Sazonov ◽  
D. Striakhilev ◽  
J. H. Chang ◽  
G. Heiler ◽  
...  
Keyword(s):  
Fill Factor ◽  
Sensor Arrays ◽  
Image Sensor ◽  
Low Noise ◽  
Active Matrix ◽  
Interlayer Dielectric ◽  
Sensor Performance ◽  
Data Line ◽  
High Fill Factor ◽  
Low K

ABSTRACTIn this paper, we report on low noise, high fill factor amorphous silicon (a-Si:H) image sensor structures for indirect radiography. Two types of the sensor arrays comprising n-i-p photodiodes and m-i-s photosensors have been fabricated. The device prototypes contain 100 × 100 pixels, with a pixel pitch of 139 μm. The active-matrix addressing is provided by low off-current TFTs. The sensors are vertically integrated onto the TFT-backplane, by implementing a 3-μm-thick low-k interlayer dielectric. This dielectric layer serves to reduce the data line capacitance and to planarize underlying topography. The detector was designed for reduced data-line resistance and parasitic coupling. Details of the device design and fabrication, along with sensor performance characteristics, are presented and discussed.

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size
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