Improvement of intelligent cyclic ADC resolution by randomization of DAC INL errors

2012 ◽  
Author(s):  
Ł. Małkiewicz
Keyword(s):  
Cyclic Adc

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

2014 ◽  
Vol 35 (3) ◽  
pp. 035005 ◽  
Author(s):  
Kaiming Nie ◽  
Suying Yao ◽  
Jiangtao Xu ◽  
Zhaorui Jiang
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Cyclic Adc

A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

2011 ◽  
Vol 32 (2) ◽  
pp. 025008 ◽  
Author(s):  
Hongliang Zhao ◽  
Yiqiang Zhao ◽  
Junfeng Geng ◽  
Peng Li ◽  
Zhisheng Zhang
Keyword(s):  
Low Power ◽  
Mismatch Correction ◽  
Cyclic Adc

An Extended-Counting Incremental Sigma–Delta ADC with Hardware-Reuse Technique

2016 ◽  
Vol 25 (05) ◽  
pp. 1650038
Author(s):  
Xinji Zeng ◽  
Jing Gao ◽  
Liu Yang ◽  
Jiangtao Xu
Keyword(s):  
Conversion Rate ◽  
Cmos Process ◽  
Digital Output ◽  
Sigma Delta ◽  
Design And Implementation ◽  
Conversion Time ◽  
Cyclic Adc ◽  
Sigma Delta Adc ◽  
Oversampling Ratio ◽  
Least Significant Bits

This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology

2021 ◽  
Author(s):  
Eiki Kayama ◽  
Kenta Mori ◽  
Maebou Taichi ◽  
Yuanchi Chen ◽  
Hao San ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Cyclic Adc

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion

2015 ◽  
Author(s):  
Yuta Mishima ◽  
Toshiki Yamada ◽  
Asato Uchiyama ◽  
Tatsuji Matsuura ◽  
Hao San ◽  
...  
Keyword(s):  
Cyclic Adc

A LOW-POWER 12-BIT 250 KS/S CYCLIC ADC FOR LONG LINE ARRAY INFRARED SENSORS READOUT CIRCUIT

2011 ◽  
Vol 20 (01) ◽  
pp. 57-70 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
PENG LI ◽  
JUNWEI JIANG ◽  
ZHISHENG ZHANG
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Clock Frequency ◽  
Infrared Sensors ◽  
Differential Nonlinearity ◽  
Line Array ◽  
Long Line ◽  
Correction Technique ◽  
Cyclic Adc

A 12-bit cyclic analog to digital converter (ADC) used in long line array infrared sensors readout circuit is presented. The architecture of a low-power amplifier shared with two groups of switched capacitors is used to reduce power consumption. By adding cross-connected switches, the amplifier's offset is effectively canceled out. The improved redundant signed digit (RSD) correction technique is employed to compensate for the error resulting from the comparator's offset in sub-ADC, and the correction technique can tolerate high level of switched capacitor mismatch error, as well. The converter manufactured with Chartered 0.35 μm CMOS process exhibits 0.92 LSB maximum differential nonlinearity (DNL) and 1.5 LSB maximum integral nonlinearity (INL). The ADC has a 69.3 dB signal to noise and distortion ratio (SNDR) at 250 kS/s sample rate and 3 MHz clock frequency. It dissipates 0.8 mW with 3.3 V supply and occupies 0.22 × 0.9 mm2.

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components

2017 ◽  
Author(s):  
Yuki Watanabe ◽  
Hayato Narita ◽  
Hiroyuki Tsuchiya ◽  
Tatsuji Matsuura ◽  
Hao San ◽  
...  
Keyword(s):  
High Accuracy ◽  
Cyclic Adc
Sign in / Sign up

Export Citation Format

Share Document