Coarse-to-fine strategy for motion estimation

1993 ◽  
Author(s):  
E. Degremont ◽  
Thomas Skordas ◽  
Serge De Paoli ◽  
A. Chehikian
Keyword(s):  
Motion Estimation ◽  
Coarse To Fine

scholarly journals BlockNet: A Deep Neural Network for Block-Based Motion Estimation Using Representative Matching

Symmetry ◽  
2020 ◽  
Vol 12 (5) ◽  
pp. 840
Author(s):  
Junggi Lee ◽  
Kyeongbo Kong ◽  
Gyujin Bae ◽  
Woo-Jin Song
Keyword(s):  
Motion Estimation ◽  
Computational Cost ◽  
Frame Rate ◽  
Global Motion ◽  
Neural Architecture ◽  
Block Motion ◽  
Block Based ◽  
Frame Rate Up Conversion ◽  
Coarse To Fine ◽  
Simple Average

Owing to the limitations of practical realizations, block-based motion is widely used as an alternative for pixel-based motion in video applications such as global motion estimation and frame rate up-conversion. We hereby present BlockNet, a compact but effective deep neural architecture for block-based motion estimation. First, BlockNet extracts rich features for a pair of input images. Then, it estimates coarse-to-fine block motion using a pyramidal structure. In each level, block-based motion is estimated using the proposed representative matching with a simple average operator. The experimental results show that BlockNet achieved a similar average end-point error with and without representative matching, whereas the proposed matching incurred 18% lower computational cost than full matching.

scholarly journals Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8
Author(s):  
Reeba Korah ◽  
J.Raja Paul Perinbam
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Motion Vector ◽  
Computational Cost ◽  
Parallel Architecture ◽  
Clock Frequency ◽  
Processing Elements ◽  
Parallel Design ◽  
Search Approach ◽  
Coarse To Fine

This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.

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