Influence of the carrier wafer during GaN etching in Cl2 plasma

2022 ◽  
Vol 40 (2) ◽  
pp. 023202
Author(s):  
Thibaut Meyer ◽  
Camille Petit-Etienne ◽  
Erwine Pargon
Keyword(s):  
Carrier Wafer ◽  
Gan Etching

High Heat Resistant Peelable Temporary Bonding Film and New Debonding System with Xe Flash Light Irradiation

2020 ◽  
Vol 2020 (1) ◽  
pp. 000302-000306
Author(s):  
Yuta Akasu ◽  
Emi Miyazawa ◽  
Tetsuya Enomoto ◽  
Yasuyuki Oyama ◽  
Shogo Sobue ◽  
...  
Keyword(s):  
Chemical Resistance ◽  
High Heat ◽  
Light Irradiation ◽  
Wafer Surface ◽  
Assembly Process ◽  
Test Vehicle ◽  
Packaging Process ◽  
Release System ◽  
Temporary Bonding ◽  
Carrier Wafer

Abstract We have developed a new temporary bonding film (TBF) and new debonding system with Xe flash light irradiation, named photonic release system, for advanced package assembly process. Since new TBF has a high Tg over 200 °C after curing and shows good chemical resistance to developer, resist stripper, and plating chemicals, no delamination, voiding, and swelling were observed after thermal and chemical treatment in the bonded structure of wafer and glass carrier. In addition, by adopting a metal-sputtered glass carrier, wafer could be debonded by Xe flash light irradiation in less than 1 ms through the glass carrier with no damage. Residual TBF on the wafer surface could be peeled off smoothly at ambient temperature without residue on the wafer. In this research, we also demonstrated the good applicability of this temporary bonding film to the typical packaging process by using test vehicle including 12 inch mold wafer and the advantage of photonic release system.

scholarly journals Metal-Assisted Chemical Etching for Anisotropic Deep Trenching of GaN Array

Nanomaterials ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 3179
Author(s):  
Qi Wang ◽  
Kehong Zhou ◽  
Shuai Zhao ◽  
Wen Yang ◽  
Hongsheng Zhang ◽  
...  
Keyword(s):  
Chemical Etching ◽  
Low Cost ◽  
Etching Rate ◽  
Surface Damage ◽  
Device Fabrication ◽  
Irreversible Damage ◽  
Catalytic Role ◽  
Metal Assisted Chemical Etching ◽  
Gan Etching

Realizing the anisotropic deep trenching of GaN without surface damage is essential for the fabrication of GaN-based devices. However, traditional dry etching technologies introduce irreversible damage to GaN and degrade the performance of the device. In this paper, we demonstrate a damage-free, rapid metal-assisted chemical etching (MacEtch) method and perform an anisotropic, deep trenching of a GaN array. Regular GaN microarrays are fabricated based on the proposed method, in which CuSO4 and HF are adopted as etchants while ultraviolet light and Ni/Ag mask are applied to catalyze the etching process of GaN, reaching an etching rate of 100 nm/min. We comprehensively explore the etching mechanism by adopting three different patterns, comparing a Ni/Ag mask with a SiN mask, and adjusting the etchant proportion. Under the catalytic role of Ni/Ag, the GaN etching rate nearby the metal mask is much faster than that of other parts, which contributes to the formation of deep trenches. Furthermore, an optimized etchant is studied to restrain the disorder accumulation of excessive Cu particles and guarantee a continuous etching result. Notably, our work presents a novel low-cost MacEtch method to achieve GaN deep etching at room temperature, which may promote the evolution of GaN-based device fabrication.

Impact of carrier wafer on etch rate, selectivity, morphology, and passivation during GaN plasma etching

2021 ◽  
Vol 39 (5) ◽  
pp. 053002
Author(s):  
Clint D. Frye ◽  
Scott B. Donald ◽  
Catherine Reinhardt ◽  
Lars F. Voss ◽  
Sara E. Harrison
Keyword(s):  
Plasma Etching ◽  
Etch Rate ◽  
Carrier Wafer

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001009-001032
Author(s):  
Mark Oliver ◽  
Jong-Uk Kim ◽  
Michael Gallagher ◽  
Zidong Wang ◽  
Janet Okada ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Spin Coating ◽  
Bonding Temperature ◽  
High Volume ◽  
Wafer Surface ◽  
Process Time ◽  
Adhesion Promoter ◽  
Excellent Thermal Stability ◽  
Carrier Wafer ◽  
Bonding Technology

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements. For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Damage-free GaN Etching by Chlorine Neutral Beam

2011 ◽  
Author(s):  
Y. Tamura ◽  
X.Y. Wang ◽  
C.H. Huang ◽  
T. Kubota ◽  
J. Ohta ◽  
...  
Keyword(s):  
Neutral Beam ◽  
Gan Etching
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