Low temperature processing and characterization of metastable anisotype heterojunction‐gate strained‐layer field‐effect transistors

1991 ◽  
Vol 9 (3) ◽  
pp. 858-862
Author(s):  
C. L. Lin ◽  
H. H. Wieder
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Strained Layer ◽  
Low Temperature Processing

Low temperature electrical characterization of metal‐nitrided oxide‐silicon field effect transistors

1993 ◽  
Vol 73 (10) ◽  
pp. 5241-5253 ◽  
Author(s):  
A. Emrani ◽  
G. Ghibaudo ◽  
F. Balestra ◽  
B. Piot ◽  
V. Thirion ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Characterization

scholarly journals Low‐Temperature Processing of Printed Field‐Effect Transistors from Sublimating‐Stabilizer Derived Oxide Nanodispersions

2019 ◽  
Vol 5 (7) ◽  
pp. 1800764
Author(s):  
Mitta Divya ◽  
Sivaramakrishnan Sethuraman ◽  
Nehru Devabharathi ◽  
Sandeep Kumar Mondal ◽  
Subho Dasgupta
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Low Temperature Processing

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

Fabrication and Characterization of GaN-based Nanostructure Field Effect Transistors

2021 ◽  
pp. 108079
Author(s):  
Dong-Hyeok Son ◽  
Terirama Thingujam ◽  
Quan Dai ◽  
Jeong-Gil Kim ◽  
Sorin Cristoloveanu ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Fabrication And Characterization
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