Product development and yield enhancement through failure analysis of integrated circuits with scanning capacitance microscopy

2003 ◽  
Vol 21 (4) ◽  
pp. 1539-1544 ◽  
Author(s):  
P. Tangyunyong ◽  
C. Y. Nakakura
Keyword(s):  
Integrated Circuits ◽  
Product Development ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Scanning Capacitance Microscopy

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

New Rapid Failure Analysis Techniques for Multilevel Metallization

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 74-77
Author(s):  
Edward I. Cole ◽  
Richard E. Anderson
Keyword(s):  
Integrated Circuits ◽  
Product Development ◽  
Failure Analysis ◽  
New Product Development ◽  
New Product ◽  
Electronics Industry ◽  
New Techniques ◽  
Analysis Techniques ◽  
Advantages And Disadvantages ◽  
Failure Site

Open interconnections on integrated circuits (ICs) are a serious and ubiquitous problem throughout the micro-electronics industry. The efforts to understand the mechanisms responsible for producing open interconnections and to develop analytical methods to localize them demonstrate the concern manufacturers have for this problem. Multiple layers of metallization not only increase the probability that an open conductor or via will occur because of the increased number of interconnections and vias but also increase the difficulty in localizing the site of the failure because upper layers may mask the failure site.Rapid failure analysis of open-conductor defects is critical in new product development and reliability assessment of ICs where manufacturing and product development delays can cost millions of dollars a day. In this article, we briefly review some standard failure analysis approaches and then concentrate on new techniques to rapidly locate open-conductor defects that would have been difficult or impossible to identify using earlier methods. Each method is described in terms of the physics of signal generation, application, and advantages and disadvantages when compared to existing methods.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

Front-End Failure Analysis of Integrated Circuits Using Scanning Capacitance Microscopy

2004 ◽  
Author(s):  
M.C. Huang ◽  
C.T. Lin ◽  
J.C. Lin
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Channel Length ◽  
Cross Sectional ◽  
Scanning Capacitance Microscopy ◽  
Front End ◽  
Low Threshold ◽  
Power Leakage ◽  
Plane View ◽  
Better Than

Abstract Scanning capacitance microscopy (SCM), a powerful technique to identify front-end defects, is also helpful in understanding failure mechanisms. This article discusses three front-end doping failure examples that were clearly identified by SCM analysis. The first example was NMOS leakage between drain and source. SCM images showed that N+ junction distortion resulted in effective channel length shortage. The second one was by-field SRAM failure with power leakage. From SCM images, it is clarified that P-well was directly short to P+ in bad die and slight P-well boundary shift to P+ was observed in good die. The third example was regarding low threshold voltage failure analysis. It illustrates that combination of plane-view and cross-sectional SCM analysis could help to diagnose the failure mechanism. The resolution and precision in SCM is better than that in chemical etching combined with SEM technique.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors

2005 ◽  
Author(s):  
M.L. Anderson ◽  
P. Tangyunyong ◽  
T.A. Hill ◽  
C.Y. Nakakura ◽  
T.J. Headley ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
New Product Development ◽  
Yield Enhancement ◽  
Product Development Process ◽  
Product Lines ◽  
Scanning Capacitance Microscopy ◽  
Transmission Electron ◽  
Complementary Techniques ◽  
Analytical Tools

Abstract By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

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