Design and Fabrication of a High Temperature Pressure Sensor

Author(s):  
Libo Zhao ◽  
Yulong Zhao ◽  
Zhuangde Jiang

Based on Silicon on Insulator (SOI) and Micro Electro Mechanical System (MEMS) technology, a single-crystal silicon piezoresistive strain gage was fabricated and constituted by silicon substrate, a thin SiO2 layer by Separation by Implantation of Oxygen (SIMOX), an optimized boron ion implantation doping layer photo lithographed to discrete piezoresistors, stress matching Si3N4 layer, and metallization scheme of Ti/Pt/Au as beam lead layer for connecting piezoresistors to be Wheatstone bridge configuration. A special buried SiO2 layer with the thickness of 367 nm was fabricated by the SIMOX technology, which replaced p-n junction to isolate the piezoresistors from the bulk silicon substrate, so this kind of single-crystal silicon strain gage can be used in many harsh fields under high temperature up to 350°C. By the single-crystal silicon strain gage packaged on the metallic circular flat diaphragm, and along with other thermal treatments and compensating methods, a high temperature pressure sensor has been developed with the pressure range of 0–120 MPa under high temperature above 200°C. The testing results show that the sensor has good static performances under 200°C and fine dynamic characteristics to meet the requirements of the modern industry, such as petroleum and chemistry, mobile industry, military industry, wind tunnels, materials processing.

Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.


2020 ◽  
pp. 100107
Author(s):  
L.G. Michaud ◽  
E. Azrak ◽  
C. Castan ◽  
F. Fournel ◽  
F. Rieutord ◽  
...  

2001 ◽  
Vol 687 ◽  
Author(s):  
H.-S. Moon ◽  
L. Anand ◽  
S. M. Spearing

AbstractSilicon in single crystal form has been the material of choice for the first demonstration of the MIT microengine project. However, because it has a relatively low melting temperature, silicon is not an ideal material for the intended operational environment of high temperature and stress. In addition, preliminary work indicates that single crystal silicon has a tendency to undergo localized deformation by slip band formation. Thus it is critical to obtain a better understanding of the mechanical behavior of this material at elevated temperatures in order to properly exploit its capabilities as a structural material. Creep tests in simple compression with n-type single crystal silicon, with low initial dislocation density, were conducted over a temperature range of 900 K to 1200 K and a stress range of 10 MPa to 120 MPa. The compression specimens were machined such that the multi-slip <100> or <111> orientations were coincident with the compression axis. The creep tests reveal that response can be delineated into two broad regimes: (a) in the first regime rapid dislocation multiplication is responsible for accelerating creep rates, and (b) in the second regime an increasing resistance to dislocation motion is responsible for the decelerating creep rates, as is typically observed for creep in metals. An isotropic elasto-viscoplastic constitutive model that accounts for these two mechanisms has been developed in support of the design of the high temperature turbine structure of the MIT microengine.


Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi ◽  
K. E. Goodson

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.


2000 ◽  
Author(s):  
John M. Maloney ◽  
Don L. DeVoe ◽  
David S. Schreiber

Abstract Thermal actuators that deflect laterally by resistive heating have been fabricated in single crystal silicon (SCS) by deep reactive ion etching (DRIE). With heights of 50 μm, these high-aspect actuators produce significantly larger forces than similar polysilicon devices. Problems with stiction are also avoided through the use of silicon-on-insulator (SOI) technology. An analytical model is applied to U-beam and V-beam actuator shapes fabricated on SOI wafers. The electrothermal component of the analysis uses an axial conduction model to predict temperature distribution; the thermomechanical component employs elastic beam theory to calculate deflection due to thermal strain. Experimental results are compared to analytical predictions. Deflections of 29 μm for a 1200 μm long, 12 μm wide V-beam actuator were observed, corresponding to a predicted force of 7.6 mN.


2017 ◽  
Vol 5 (3) ◽  
Author(s):  
Tsuneo Kurita ◽  
Koji Miyake ◽  
Kenji Kawata ◽  
Kiwamu Ashida ◽  
Tomohisa Kato

The aim of this research is to develop a combined polishing technology for single-crystal silicon carbide (SiC) wafers, which is known to be difficult to process due to its high hardness. This paper proposes a combined polishing method based on converting SiC into a material with a relatively low hardness and then polishing this material using abrasive particles with a higher hardness. An electrochemical technique was tried to reduce the hardness of SiC. The effectiveness of the combined technique is experimentally demonstrated. In addition, the temporal changes of the thickness of SiO2 layer and the relationship between the electrochemical machining current and the thickness of SiO2 layer are shown.


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