Reliability of Interconnections Made of Sintered Silver Nano Particles

2015 ◽  
Author(s):  
Przemyslaw K. Matkowski ◽  
Tomasz Falat ◽  
Andrzej Moscicki
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Nano Particles ◽  
Circuit Board ◽  
X Ray ◽  
Detection Failure ◽  
X Ray Computed ◽  
Sintered Silver

This study investigates the effect of silver paste composition on reliability of sintered silver interconnections. The interconnections are formed between SMD 1206 chip jumpers and electroless nickel immersion gold (ENIG) coating of FR4 printed circuit board (PCB) solder pads. They are made of pastes that vary in their composition (various proportions of micro and nano particles). The sintering process was conducted in convective oven. After the process the interconnections were subjected to X-Ray inspection in order to characterize the structure of interconnections (presence of voids, total surface of interconnection etc.). During accelerated reliability tests the PCBs were subjected to combined temperature cycling and vibration loading. During the tests daisy chains of interconnections were connected to dedicated programmable multichannel event detector developed in LIPEC lab. The event detector is able to detect and store information about object condition based on the real-time resistance measurements and applied novel algorithm of event detection. Failure modes were confirmed by using X-Ray computed tomography. The paper presents results of comparative Weibull analysis.

Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Jia Xi ◽  
Xinduo Zhai ◽  
Jun Wang ◽  
Donglun Yang ◽  
Mao Ru ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
High Stress ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Element Analysis ◽  
Drop Tests ◽  
Feni Alloy

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Failure Analysis on BGA U45 on Soldered Balls

2020 ◽  
Author(s):  
Miguel Angel Neri Flores ◽  
Gregorio Vázquez Olvera
Keyword(s):  
Computed Tomography ◽  
Failure Analysis ◽  
Cross Sections ◽  
Printed Circuit Board ◽  
Intermetallic Layer ◽  
Circuit Board ◽  
X Ray ◽  
Printed Circuit ◽  
Solder Balls ◽  
X Ray Computed

Abstract This paper presents a failure analysis to determine the origin of the failure on the soldered balls of one BGA soldered to a Printed circuit board, presenting Intermittency on the soldered joints, by Visual inspection, X ray inspection, Computed Tomography(CT), Cross-section analysis, Scanning Electron Microscopy, and Energy dispersive spectroscopy, determined the failure located on soldered balls of the BGA was caused by cracks that run along the Intermetallic layer formed between the solder balls and the copper pads of the printed circuit board, that were located near the BGA corners. With X ray computed Tomography we can analyze all the soldered balls of the BGA, by "virtual" cross-sections on the soldered joints without damage on the sample.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

Process-Induced Thermal Effect on Packaging Yield of RF MEMS Switches

2002 ◽  
Author(s):  
Lei L. Mercado ◽  
Shun-Meen Kuo ◽  
Tien-Yu Tom Lee ◽  
Russ Lee
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Rf Mems ◽  
Electrostatic Force ◽  
Circuit Board ◽  
Mems Switches ◽  
Rf Mems Switches ◽  
Significant Performance ◽  
And Performance ◽  
Lower Temperature

RF MEMS switches offer significant performance advantages in high frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320°C. The assembled packages were then attached to a printed circuit board at 220°C. During the process, some switches failed due to electrical shorting. More interestingly, more failures were observed at the lower temperature of 220°C rather than 320°C. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance.

A Novel Discrete Passives Integration on Organic Substrate

2005 ◽  
Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Electrical Performance ◽  
Core Material ◽  
Bottom Surface ◽  
Passive Components ◽  
Printed Circuit

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.

scholarly journals Locate faulty components by IR based Direct Current Injection method with Analog Signature Analysis

2021 ◽  
Author(s):  
Zhifeng Zhu ◽  
Paul Leone
Keyword(s):  
Direct Current ◽  
Printed Circuit Board ◽  
Failure Modes ◽  
High Efficiency ◽  
Circuit Board ◽  
Signature Analysis ◽  
Printed Circuit Board Assembly ◽  
Component Failure ◽  
Printed Circuit ◽  
Circuit Board Assembly

Abstract This article describes a method to integrate Analog Signature Analysis (ASA) into IR based Direct Current Inject method (IRDCI) for Printed Circuit Board Assembly failure analysis, which extends IRDCI application from diagnostic shorted power rails to any measurement locations that show signature differences. Also, it extends the application of component failure modes from electrical short to breakdown or degradation that can be identified by signature comparison and still keep high efficiency to eliminate the needs to guess and remove suspected faulty components one by one from the board to validate.

Effect of Blast Wave on Intermetallics Formation, Hardness and Reduced Modulus Properties of Solder Joints

2020 ◽  
Vol 307 ◽  
pp. 31-36
Author(s):  
Nur Shafiqa Safee ◽  
Wan Yusmawati Wan Yusoff ◽  
Ariffin Ismail ◽  
Norliza Ismail ◽  
Maria Abu Bakar ◽  
...  
Keyword(s):  
Surface Finish ◽  
Test Performance ◽  
Printed Circuit Board ◽  
Microstructural Analysis ◽  
Electroless Nickel ◽  
Optical Microscope ◽  
Circuit Board ◽  
Reduced Modulus ◽  
Free Solder ◽  
Tin Silver Copper

Tin-Silver-Copper (SnAgCu) lead-free solder on Electroless Nickel Immersion Gold (ENiG) and Immersion Tin (ImSn) surface finish printed circuit board was subjected to blast test. A variation of intermetallic compounds (IMC) layer, hardness and reduced modulus of soldered sample exposed to blast test were intensively investigated using optical microscope and nanoindentation machine. Formation of IMCs due to reaction between solder and substrate during blast test provided deleterious effect of metallurgical bond strength and reliability on the solder joint. Microstructural analysis was evaluated via Infinite Focused Microscope (IFM). The findings of these studies indicate that best surface finished for blast test performance was not necessarily the best surface finish for optimum reliability. ENiG and ImSn surface finish can be advantage or a disadvantage depending on the application, package and reliability requirements. As a result, most component assemblers are using ENiG and ImSn in order to improve solderability as well as the wettability between solder and the substrate and to meet various package requirements.

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