High Field Breakdown of Carbon Nanotube Network Transistors

Author(s):  
Man Prakash Gupta ◽  
Ashkan Behnam ◽  
David Estrada ◽  
Eric Pop ◽  
Satish Kumar

We develop and employ a self-consistent electro-thermal model to study the high field breakdown of carbon nanotube (CNT) network thin film transistors (CN-TFTs). We investigate the effects of the CNT alignment angle and length distribution on the breakdown process caused by excessive self-heating. We examine relevant breakdown characteristics such as the peak current and corresponding voltage and power in relation to these two network parameters. We find that the breakdown behavior can significantly vary with respect to the CNT length and alignment distribution even when the network density is kept the same. Results suggest that an optimum alignment (∼ 65°) can be found for a network with constant CNT lengths to obtain higher current/power without setting off an early breakdown. When both CNT length and alignment angle are varied, we find that networks with higher average CNT length have lower optimum alignment such that doubling the average CNT length lowers the optimum alignment angle by half. Therefore these network parameters need to be carefully selected to achieve greater thermal reliability and higher electrical performance.

ACS Nano ◽  
2012 ◽  
Vol 7 (1) ◽  
pp. 482-490 ◽  
Author(s):  
Ashkan Behnam ◽  
Vinod K. Sangwan ◽  
Xuanyu Zhong ◽  
Feifei Lian ◽  
David Estrada ◽  
...  

2020 ◽  
Vol 15 (12) ◽  
pp. 1442-1449
Author(s):  
Hayk Khachatryan ◽  
Kyoung-Bo Kim ◽  
Moojin Kim

The electrical, thermal, chemical, and mechanical characteristics of a flexible electrode consisting of carbon nanotubes on paper were investigated under various conditions. The main driving motivation was to develop a durable and flexible film for conductive electrode applications. The general characteristics of the electrode based on carbon nanotubes were found to be sensitive to coating sequence and aging temperature and duration. The number of coatings can be used to tune network density and form a well entangled carbon nanotube layer on paper. Aging temperature was found to be critical to electrical characteristics, and 60 °C was determined to be the optimal aging temperature. At higher temperatures, calcium oxide contained in the paper may form carbonates, which change the structure of the paper, and the carbon nanotubes can be oxidized, which led to reduced electrical performance. The mechanical durability tests revealed that the electrode was functional up to a 3 mm bending radius.


2013 ◽  
Vol 24 (40) ◽  
pp. 405204 ◽  
Author(s):  
Man Prakash Gupta ◽  
Ashkan Behnam ◽  
Feifei Lian ◽  
David Estrada ◽  
Eric Pop ◽  
...  

2010 ◽  
Vol 16 (6) ◽  
pp. 955-959 ◽  
Author(s):  
Hui Cao ◽  
Zhiyin Gan ◽  
Qiang Lv ◽  
Han Yan ◽  
Xiaobin Luo ◽  
...  

2013 ◽  
Vol 747 ◽  
pp. 526-529
Author(s):  
Bo Yuan Su ◽  
Meng Chun Chen ◽  
Sheng Yuan Chu ◽  
Yang Der Juang

In this paper, the carbon nanotube was well dispersed into the poly (3,4-ethylenedioxythiophene) poly (styrenesulfonate) (PEDOTPSS) solution with a best concentration of 4 mg/ml. The prepared sol was spun on poly (ether sulfone) (PES) substrates, showing sheet resistance as low as 19.8 Ω/sq and the high average transmittance over 90 %. The change in optical and electrical properties due to poly (ether sulfone) (PES) substrate was investigated to understand the failure mechanisms. For realizing the bending effect on electrical performance, the pre-deposited ZnO buffer was introduced to improve the deterioration during the repeated bending test. The composite polymer enhanced the electrical conductivity with less detrimental effect on the optical transparency, which suggests the potential transparent conductive films for use in developing optical and electrical device.


Author(s):  
Tiantao Lu ◽  
Ankur Srivastava

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.


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