Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure

2007 ◽  
Author(s):  
Chan-Yen Chou ◽  
Chung-Jung Wu ◽  
Hsiu-Ping Wei ◽  
Ming-Chih Yew ◽  
Chien-Chia Chiu ◽  
...  
Keyword(s):  
Thermal Management ◽  
Power Density ◽  
High Power ◽  
Hot Spot ◽  
Junction Temperature ◽  
High Power Density ◽  
Solder Paste ◽  
Operation Temperature ◽  
Test Board ◽  
Chip Carrier

In this paper, a thermal enhanced design for a high power density system in package (SiP) is proposed to resolve the challenge faced by the packaging research community in eliminating the hot spot and reducing the junction temperature in a high operation temperature. The SiP structure includes seven sub-chips which are attached to the chip carrier. The dissipated heat is conducted to the metal slug by thermal vias, while some heat is conducted to the pads by metal traces. Finally, the whole module is connected to the test board by solder paste material. In the thermal enhanced design, a highly conductive material such as solder paste is applied to make an attachment between the chip carrier and the highest power density chip (the power amplifier chip). Besides, some thermal vias are constructed to conduct the dissipated heat from the chip carrier to the metal slug. The new structure greatly improves the thermal performance of the SiP structure. Moreover, the hot spot on the chip carrier is also eliminated in this thermal enhanced SiP structure.

Near-junction heat spreaders for hot spot thermal management of high power density electronic devices

2019 ◽  
Vol 126 (16) ◽  
pp. 165113
Author(s):  
R. Soleimanzadeh ◽  
R. A. Khadar ◽  
M. Naamoun ◽  
R. van Erp ◽  
E. Matioli
Keyword(s):  
Thermal Management ◽  
Power Density ◽  
High Power ◽  
Hot Spot ◽  
Electronic Devices ◽  
High Power Density ◽  
Heat Spreaders

scholarly journals Advanced Thermal Management for High Power Density Electronics

2017 ◽  
Author(s):  
Nenad Miljkovic ◽  
Thomas Foulkes ◽  
Junho Oh ◽  
Patrick Birbarah ◽  
Robert Pilawa-Podgurski ◽  
...  
Keyword(s):  
Thermal Management ◽  
Power Density ◽  
High Power ◽  
High Power Density

Embedded Microjets for Thermal Management of High Power-Density Electronic Devices

2019 ◽  
Vol 9 (2) ◽  
pp. 269-278 ◽  
Author(s):  
Stephen M. Walsh ◽  
Bernard A. Malouin ◽  
Eric A. Browne ◽  
Kevin R. Bagnall ◽  
Evelyn N. Wang ◽  
...  
Keyword(s):  
Thermal Management ◽  
Power Density ◽  
High Power ◽  
Electronic Devices ◽  
High Power Density

Effects of solder paste on thermal and optical performance of high-power ThinGaN white LED

2018 ◽  
Vol 30 (3) ◽  
pp. 182-193 ◽  
Author(s):  
Muna E. Raypah ◽  
Mutharasu Devarajan ◽  
Fauziah Sulaiman
Keyword(s):  
Thermal Resistance ◽  
Thermal Management ◽  
High Power ◽  
Junction Temperature ◽  
Critical Parameters ◽  
White Led ◽  
Solder Paste ◽  
Optical Performance ◽  
Content Type ◽  
Color Shift

Purpose Thermal management of high-power (HP) light-emitting diodes (LEDs) is an essential issue. Junction temperature (TJ) and thermal resistance (Rth) are critical parameters in evaluating LEDs thermal management and reliability. The purpose of this paper is to study thermal and optical characteristics of ThinGaN (UX:3) white LED mounted on SinkPAD by three types of solder paste (SP): No-Clean SAC305 (SP1), Water-Washable SAC305 (SP2) and No-Clean Sn42/Bi57.6/Ag0.4 (SP3). Design/methodology/approach Thermal transient tester (T3Ster) machine is used to determine TJ and total thermal resistance (Rth–JA). In addition, the LED’s optical properties are measured via thermal and radiometric characterization of power LEDs (TeraLED) system. The LED is mounted on SinkPAD using SP1, SP2 and SP3 by stencil printing to control a thickness of SP and reflow soldering oven to minimize the number of voids. The LED with SP1, SP2 and SP3 is tested at various input currents and ambient temperatures. Findings The results indicate that at high input current, which equals to 1,200 mA, Rth–JA and TJ, respectively, are reduced by 30 and 17 per cent between SP1 and SP2. At same current value, Rth–JA and TJ are minimized by 42 and 25 per cent between SP1 and SP3, respectively. In addition, at an ambient temperature of 85°C, Rth–JA and TJ are decreased by 34 and 7 per cent between SP1 and SP2, respectively. Similarly, the reduction in Rth–JA and TJ between SP1 and SP3 is 44 and 10 per cent, respectively. Luminous flux, luminous efficacy and color shift of the LED with the three types of SPs are compared and discussed. It is found that the SP1 improves the chromatic properties of the LED by increasing the overall light efficiency and decreasing the color shift. Originality/value Thermal and optical performance of ThinGaN LEDs mounted on SinkPAD via three types of SPs is compared. This investigation can assist the research on thermal management of HP ThinGaN-based LEDs.

DBC Switch Module for Management of Temperature and Noise in 220-W/in3 Power Assembly

2014 ◽  
Vol 2014 (1) ◽  
pp. 000744-000750 ◽  
Author(s):  
Woochan Kim ◽  
Jongwon Shin ◽  
Khai D. T. Ngo
Keyword(s):  
Power Density ◽  
High Power ◽  
Temperature Rise ◽  
Junction Temperature ◽  
High Power Density ◽  
Switching Noise ◽  
Turn On ◽  
The Right ◽  
Negative Coupling ◽  
Switch Module

Achieving high power density is a challenge in the presence of stringent specifications on temperature rise and switching noise. Integration of the DBC module with PCB mother board was found to be the right approach to achieve 220-W/in3 power density, 2-kW output power, and 48.9°C junction-temperature rise. The reduced layout inductance (2.89-nH) at the source and the negative coupling between source and drain layout inductances suppressed turn-off noise. The prototyped dc-dc boost converter switched between 400 kHz to 1 MHz without self-turn-on problems and efficiency was 98.4 % by employing DBC switch module.

scholarly journals THE ADVANTAGES OF EVAPORATION IN MICRO-SCALE CHANNELS TO COOL MICROELETRONIC DEVICES

2007 ◽  
Vol 6 (2) ◽  
pp. 34 ◽  
Author(s):  
G. Ribatski ◽  
L. Cabezas-Gómez ◽  
H. A. Navarro ◽  
J. M. Saíz-Jabardo
Keyword(s):  
Specific Heat ◽  
Thermal Management ◽  
Power Density ◽  
High Power ◽  
Heat Sink ◽  
Flow Boiling ◽  
Electronic Devices ◽  
Management Systems ◽  
High Power Density ◽  
Micro Scale

In this paper, the importance of the development of new high power density thermal management systems for electronic devices is assessed. It is described the new heat sink technologies under development to be used in the cooling of microprocessors. The main difficulties to be overcome before the spreading of one specific heat sink configuration are identified. At the end, it is concluded that a heat sink based on flow boiling in micro-scale channels is the most promising approach.

Full Scale Simulation of an Integrated Monolithic Heat Sink for Thermal Management of a High Power Density GaN-SiC Chip

2015 ◽  
Author(s):  
Tanya Liu ◽  
Farzad Houshmand ◽  
Catherine Gorle ◽  
Sebastian Scholl ◽  
Hyoungsoon Lee ◽  
...  
Keyword(s):  
Heat Transfer ◽  
Thermal Management ◽  
Power Density ◽  
Mass Flow ◽  
High Power ◽  
Heat Sink ◽  
High Power Density ◽  
Flow Rates ◽  
Mass Flow Rates ◽  
Insight Into

Advances in manufacturing techniques are inspiring the design of novel integrated microscale thermal cooling devices seeking to push the limits of current thermal management solutions in high heat flux applications. These advanced cooling technologies can be used to improve the performance of high power density electronics such as GaN-based RF power amplifiers. However, their optimal design requires careful analysis of the combined effects of conduction and convection. Many numerical simulations and optimization studies have been performed for single cell models of microchannel heat sinks, but these simulations do not provide insight into the flow and heat transfer through the entire device. This study therefore presents the results of conjugate heat transfer CFD simulations for a complex copper monolithic heat sink integrated with a 100 micron thick, 5 mm by 1 mm high power density GaN-SiC chip. The computational model (13 million cells) represents both the chip and the heat sink, which consists of multiple inlets and outlets for fluid entry and exit, delivery and collection manifold systems, and an array of fins that form rectangular microchannels. Total chip powers of up to 150 W at the GaN gates were considered, and a quarter of the device was modeled for total inlet mass flow rates of 1.44 g/s and 1.8 g/s (0.36 g/s and 0.45 g/s for the quarter device), corresponding to laminar flow at Reynolds numbers between 19.5 and 119.3. It was observed that the mass flow rates through individual microchannels in the device vary by up to 45%, depending on the inlet/outlet locations and pressure drop in the manifolds. The results demonstrate that full device simulations provide valuable insight into the multiple parameters that affect cooling performance.

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