Evolution of Die Stress and Delamination During Thermal Cycling of Flip Chip Assemblies

2005 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Three Dimensional ◽  
Shear Stresses ◽  
Thermal Cycles ◽  
Surface Stresses ◽  
Stress Changes ◽  
Die Surface ◽  
Delamination Propagation

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete three-dimensional silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from −40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. Through these measurements, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.

Measurement and Simulation of Moisture Induced Die Stresses in Flip Chip on Laminate Assemblies

2015 ◽  
Author(s):  
Quang Nguyen ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Moisture Absorption ◽  
Moisture Diffusion ◽  
Shear Stresses ◽  
Experimental Measurements ◽  
Normal Stresses ◽  
Long Term Storage ◽  
Stress Changes ◽  
Term Storage

In this work, an investigation has been performed on hygrothermally induced die stresses in flip chip assemblies caused by moisture absorption by the underfill encapsulant. Silicon test chips were first applied to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The sample die stresses were first measured after underfill encapsulation and cure, and then subsequently after long term storage (10 years) at room temperature and ambient humidity. The assemblies were then exposed to and 85 °C and 85% RH high humidity harsh environment for various durations, and the die stresses were evaluated as a function of the exposure time. Finally, reversibility tests were conducted to see whether the effects of moisture uptake were permanent. After long term storage, the experimental measurements showed that the normal stresses in the flip chip die relaxed significantly, while the shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposure had strong effects, generating tensile die normal stress changes of up to 30 MPa in the flip chip assemblies. Thus, the initial compressive die normal stresses due to flip chip assembly were found to relax significantly during the moisture exposure. Upon fully redrying, it was observed that the moisture-induced stress changes were fully recovered. The results of the experimental measurements were subsequently correlated with predictions from finite element numerical simulations. When performing moisture diffusion modeling, the conventional method is to use a thermal analogy based on the similarity of governing equations of heat transfer and moisture diffusion. However, this method has some drawbacks including giving incorrect results when dealing with time- and temperature-dependent problems or discontinuities in the moisture concentrations at material boundaries. In this study, we have used a new feature in ANSYS v14 to perform coupled multi-physics simulations of the moisture diffusion process without the aforementioned limitations. The simulation results were found to show strong correlations with experimental measurements.

Effect of hourglass shape solder joints on underfill encapsulation process: numerical and experimental studies

2020 ◽  
Vol 32 (3) ◽  
pp. 147-156
Author(s):  
Muhammad Naqib Nashrudin ◽  
Zhong Li Gan ◽  
Aizat Abas ◽  
M.H.H. Ishak ◽  
M. Yusuf Tura Ali
Keyword(s):  
Solder Joint ◽  
Numerical Method ◽  
Flip Chip ◽  
Solder Joints ◽  
Experimental Studies ◽  
Three Dimensional ◽  
Cross Sectional ◽  
Content Type ◽  
Filling Time ◽  
Encapsulation Process

Purpose In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method. Design/methodology/approach Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results. Findings Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints. Practical implications This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages. Originality/value LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

A Procedure for Automated Shape and Life Prediction in Flip-Chip and BGA Solder Joints

1996 ◽  
Vol 118 (3) ◽  
pp. 127-133 ◽  
Author(s):  
G. Subbarayan
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Life Prediction ◽  
Flip Chip ◽  
Solder Joints ◽  
Three Dimensional ◽  
Reliability Estimation ◽  
Element Mesh ◽  
Shape Prediction ◽  
Dimensional Finite Element

In this paper, a three-dimensional shape prediction model and a finite element solution procedure for flip-chip and BGA solder joints are developed. The developed system is capable of calculating the solder joint geometry and the fatigue life automatically without any intervention from the user. The automation achieved will enable fast reliability estimation and improved accuracy, since the two-dimensional finite element mesh used for solder shape prediction is used to generate the three-dimensional finite element mesh for stress analysis. The implementation of the procedure is verified using the solution for a flip-chip joint from literature, and the capability of the code is demonstrated on a hypothetical three-dimensional solder joint with square pads that are rotated with respect to each other, and offset from each other. The system developed in the study represents the first instance of an integrated, automated finite element procedure for both shape and fatigue life prediction in general three-dimensional solder joints. The automation achieved in the system enables fast reliability estimation in a design environment, and the optimal design of flip-chip and BGA solder joint configurations for maximum life.

The Nature of Centroidal Locus in Misaligned Flip-Chip Solder Joints

1997 ◽  
Vol 119 (3) ◽  
pp. 156-162
Author(s):  
G. Subbarayan ◽  
A. Deshpande
Keyword(s):  
Solder Joint ◽  
Cross Sections ◽  
Flip Chip ◽  
Solder Joints ◽  
Three Dimensional ◽  
Diameter Ratio ◽  
Straight Line ◽  
Dimensional Models ◽  
The Cross ◽  
Three Dimensional Models

The self-alignment mechanism of molten flip-chip solder joints is being increasingly used in passive alignment of optoelectronic devices. For these applications, three-dimensional models of misaligned solder joints are necessary to understand the effect of solder joint design parameters on self alignment. To reduce the complexity of fully three-dimensional models, intuitively reasonable assumptions are often made in their theoretical development. Two such assumptions for misaligned flip-chip solder joints with circular pads are that the locus of centroids is a straight line and that the cross sections are circular in shape. In the present paper, the limits of validity of these two assumptions are explored. In general, if either the top and bottom pad radii are identical, or if there is no misalignment between the pads, then the centroidal locus is a straight line and the cross sections are circular. The extent of deviation from straight line centroidal locus or circular cross section depends on the ratio of the top and bottom pad radii and on the extent of misalignment between the pads. For a misalignment equal to 20 percent of the solder joint height and a joint with 90 percent pad diameter ratio, the deviation from straight line locus is 7 percent and the deviation from circularity is less than 1 percent. However, as the pad ratio is decreased to 50 percent, and as the misalignment is increased to 100 percent, the deviation in centroidal locus increases to 43 percent and the deviation from circularity increases to 33 percent. Thus, straight line locus and circular cross sections are reasonable assumptions for flip-chip solder joints provided the pad diameter ratio and misalignment are small.

Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

2003 ◽  
Author(s):  
Guo-Quan Lu ◽  
Xingsheng Liu ◽  
Sihua Wen ◽  
Jesus Noel Calata ◽  
John G. Bai
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Mechanical Stresses ◽  
Flexible Substrates ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Reliability Of Solder Joints

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.

Stresses in Area Array Assemblies Subjected to Thermal Cycling

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Die Surface ◽  
Test Chips

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly

2013 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Three Dimensional ◽  
Power Cycling ◽  
Die Stress ◽  
Test Chips ◽  
Resistance Data ◽  
Critical Locations

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

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