Solder Joint Reliability Prediction of Flip Chip Packages Under Shock Loading Environment

2005 ◽  
Author(s):  
Wei Keat Loh ◽  
Luke J. Garner
Keyword(s):  
Solder Joint ◽  
Shock Loading ◽  
Joint Damage ◽  
Surface Strain ◽  
Temperature Cycle ◽  
Solder Joint Reliability ◽  
Joint Performance ◽  
Joint Reliability ◽  
Test Board ◽  
Wide Range

Solder joint reliability under shock loading condition has been a concern over the years especially with constant reductions in the characteristic dimensions of the package and the solder joint. With the impeding transition to lead free solder, attention has moved from temperature cycle failure to mechanical shock failure. A method has been developed that employs a specially designed shock test board (STB) to characterize the solder joint performance as a function of board surface strain. This unique test board can be adapted to a wide range of test and boundary conditions. Using this board, a range of shock inputs is tested to establish correlation of the dynamic response and solder joint damage severity. The effects of package size, board thickness, and solder ball pitch are included in this paper to highlight the critical design factors for solder joint reliability in shock. This method can be used to characterize solder joint performance at the component level, early in development. One can also provide board strain based design limits guide system design and prevent late discovery of solder joint issues. Modal analysis based finite element models have been used to supplement understanding of the board response. The model demonstrates good correlation of the strain on the board and the stresses developed in the solder joint. The modeling data also suggested that the maximum principal stress at the solder joint face is a good failure criterion as it maps well with the actual failure locus found.

The Characterization of Damage Propagation of BGA Flip-Chip Electronic Packages Under Mechanical Shock Loading

2009 ◽  
Author(s):  
Kayleen L. E. Helms ◽  
Ketan R. Shah ◽  
Dan Gerbus ◽  
Vasu S. Vasudevan ◽  
Jagadeesh Radhakrishnan ◽  
...  
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Shock Loading ◽  
Lead Free ◽  
Electronic Packages ◽  
Mechanical Shock ◽  
Reliability Testing ◽  
Solder Joint Reliability ◽  
Damage Propagation ◽  
Joint Reliability

Increasing power and I/O demands in HDI (high density interconnect) components coupled with the industry-wide conversion to lead-free products has introduced additional risk for solder joint reliability (SJR) of BGA (ball grid array) Flip-Chip electronic packages. One particular concern is SJR under mechanical shock (dynamic bend) loading. While leaded alloys provided good performance in shock for many years due to the unparalleled ability of lead’s slip systems to absorb the energy in shock events, lead-free alloys cannot provide the same benefit. To mitigate this risk, better approaches for understanding damage propagation are needed to enable better design to limit and reduce the SJR risk during shipping and end-user handling. To this end, a characterization study is undertaken to monitor damage progression at the second-level interconnect in BGA’s on flip-chip electronic packages during mechanical shock loading. The study uses a board-level, strain-monitoring approach plus the dye and peel failure analysis technique to track the initiation and propagation of solder joint cracks under loading. The approach being used differs from conventional reliability testing in that both design and load variables are used to quantify damage growth and strain response to bridge the understanding of design feature impact to traditional reliability testing. The scope of the study includes investigating the impact of such factors as package placement, board layout, and enabling load on the monitored board strain and the damage propagation observed. From this study, directions and design guidelines for improving solder joint reliability of future BGA’s on flip-chip electronic packages under mechanical shock loading conditions are proposed.

Power Allocation Towards Hermetic Solder Joint Health of High Powered MEMS Chip for Harsh Environment Applications

2011 ◽  
Author(s):  
Siddharth Bhopte ◽  
Parthiban Arunasalam ◽  
Fadi Alsaleem ◽  
Arvind Rao ◽  
Nataraj Hariharan
Keyword(s):  
Solder Joint ◽  
Power Allocation ◽  
Thermal Stresses ◽  
Pressure Sensors ◽  
Test Method ◽  
Solder Joint Reliability ◽  
Metal Substrates ◽  
Joint Reliability ◽  
Wide Range ◽  
Significant Difference

Solders have been utilized extensively in the MEMS packaging industry to create vacuum or hermetic seals in a variety of applications. MEMS technology is finding applications in wide range of products like pressure sensors, actuators, flow control devices etc. For many harsh low temperature environment applications, like commercial refrigeration systems, MEMS based pressure sensors and flow actuators are directly mounted on to metal substrates using solders to create hermetic sealing. Solders attaching silicon devices directly to metal substrates may be subjected to very high thermal stresses due to significant difference in thermal expansion coefficients during chip operation or environment temperatures. In this paper, case study of a high powered MEMS chip (referred in the paper as die) operating in a commercial refrigeration system is presented. Accelerated test method for qualifying solder joint for high pressure applications is briefly discussed. Lab experiments showing typical refrigeration cycle thermal load on solder joint are presented. Based on the study, concepts of die power toggling and power allocation towards enhancing hermetic solder joint reliability are discussed. Detailed numerical case studies are presented to quantify the improvement in solder joint reliability due to the proposed concept.

Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Experimental Evaluation ◽  
Flip Chip ◽  
Solder Joint Reliability ◽  
Snagcu Solder ◽  
Joint Reliability
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