Measurement of Local Residual Stress of a Flip Chip Structure Using a Stress Sensing Chip

2005 ◽  
Author(s):  
Nobuki Ueta ◽  
Hideo Miura
Keyword(s):  
Residual Stress ◽  
Polycrystalline Silicon ◽  
Flip Chip ◽  
Sensor Chip ◽  
Element Analysis ◽  
Strong Function ◽  
Chip Technology ◽  
Stress Sensing ◽  
Periodic Stress ◽  
Polycrystalline Silicon Films

Local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length. Each strain gauge was made of polycrystalline silicon films deposited on a silicon wafer. The periodic stress distribution was measured at a surface of the sensor chip between two bumps. Five gauges were aligned at a interval of 20-μm between the bumps. When the thickness of the chip was less than 200 μm, the amplitude of the stress increased drastically, as was predicted by a finite element analysis. The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 μm. The amplitude of the stress is a strong function of the thickness of a silicon chip and the intervals of the bumps.

Dominant Structural Factors of Local Residual Stress in Three-Dimensionally Stacked LSI Chips Mounted Using Flip Chip Technology

2007 ◽  
Author(s):  
Nobuki Ueta ◽  
Hideo Miura
Keyword(s):  
Residual Stress ◽  
Stress Distribution ◽  
Flip Chip ◽  
Stress And Strain ◽  
Structural Factors ◽  
Chip Technology ◽  
Average Residual ◽  
Reliable Performance ◽  
Stress Sensing ◽  
Periodic Stress

Since mechanical stress and strain change both electronic functions and reliability of LSI chips, it has become strongly important to control the residual stress and strain in them to assure their reliable performance. In this study, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps. The average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps between an upper and a bottom interconnection layer. However, the residual stress of the top chip with a free surface is not affected by the bump alignment in lower interconnection layers. It is very important, therefore, to optimize the thickness of a chip and other structural factors as mentioned above to control not only the average residual stress but also the amplitude of the periodic stress. Finally, the estimated stress distribution in the stacked two chips was proved in detail by the experiment using stress-sensing chips with 2μm long strain gauges consisted of single-crystalline Si.

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

Polycrystalline Silicon Films for Microelectromechanical Devices

1995 ◽  
Vol 403 ◽  
Author(s):  
H. Kahn ◽  
S. Stemmer ◽  
R. L. Mullen ◽  
M. A. Huff ◽  
A. H. Heuer
Keyword(s):  
Residual Stress ◽  
Polycrystalline Silicon ◽  
Microelectromechanical Systems ◽  
Device Fabrication ◽  
Process Equipment ◽  
Boron Doped ◽  
Microelectromechanical Devices ◽  
Polysilicon Films ◽  
Polycrystalline Silicon Films

AbstractPolycrystalline silicon is the most widely used structural material for surface micromachined microelectromechanical systems (MEMS). There are many advantages to using thick polysilicon films; however, due to process equipment limitations, these devices are typically fabricated from polysilicon films less than 3 μm thick. In this work, microelectromechanical test structures were designed and processed from thick (up to 10 μm) in situ boron-doped polysilicon films. The elastic modulus of these films was about 150 GPa, independent of film thickness. The thermal oxidation of the polysilicon induced a compressive stress into the top surface of the films, which was detected as a residual stress in the polysilicon after the device fabrication was complete.

Finite element analysis of lidded flip-chip packages: A study on the impact of thermal interface material compressibility and stress-free conditions on modeling predictions

2015 ◽  
Vol 2015 (1) ◽  
pp. 000151-000156
Author(s):  
Tuhin Sinha
Keyword(s):  
Flip Chip ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Element Analysis ◽  
Thermal Interface ◽  
Strong Function ◽  
Linear Elastic ◽  
Fea Modeling ◽  
Predicted Values ◽  
The Impact

In this paper, we present the effects of assumptions made about the constitutive behavior of a cured, silicone gel type thermal interface material (TIM) and the package stress-free conditions on FEA modeling predictions. The focus will be on the deformations (or warpage) predicted by the models for lidded flip-chip packages. It is critical for such warpage predictions to be close to experimental measurements for accurate projection of mechanical stresses and strains in a package. Digital Image Correlation (DIC) warpage measurements on flip-chip modules are compared against the predicted values and the impact of above-mentioned assumptions will be discussed. It will be shown that the TIM mechanical and thereby, thermal degradation is a strong function of the TIM compressibility and stress-free condition assumptions. Bounds of non-linear elastic modeling technique for the TIM and guidelines for conducting numerical analysis for lidded flip-chip packages will be provided.

Lpcvd Polycrystalline Silicon Thin Films: The Evolution of Structure, Texture and Stress

1990 ◽  
Vol 202 ◽  
Author(s):  
P. Krulevitch ◽  
Tai D. Nguyen ◽  
G. C. Johnson ◽  
R. T. Howe ◽  
H. R. Wenk ◽  
...  
Keyword(s):  
Thin Films ◽  
Residual Stress ◽  
Compressive Stress ◽  
Polycrystalline Silicon ◽  
Amorphous State ◽  
Processing Conditions ◽  
Columnar Microstructure ◽  
Silicon Thin Films ◽  
Evolution Of Structure ◽  
Polycrystalline Silicon Films

ABSTRACTAn investigation of undoped LPCVD polycrystalline silicon films deposited at temperatures ranging from 605 to 700 C and silane pressures from 300 to 550 mTorr revealed large variations in stress with processing conditions and a correlation between stress and texture. TEM and HRTEM analysis show that morphology differences also exist. At lower temperatures (≈605 C) and higher pressures (≈400 mTorr), the films appear to deposit in an amorphous state and crystallize during the deposition to form microstructures characterized by equi-axed grains, tensile residual stress, and a texture with {110} and {11/} (/=2 or 3) components. Higher temperatures (between 620 and 650 C) produce films that nucleate at the Si02 interface, creating a {110} oriented columnar microstructure. At 700 C, the grains are still columnar, but the dominant texture is {100}. Films deposited at temperatures greater than 620 C exhibit compressive stress, and some contain regions of hexagonal silicon. This paper proposes possible causes of the varying stresses, textures, and microstructures in the films.

Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique

1998 ◽  
Vol 120 (3) ◽  
pp. 309-313 ◽  
Author(s):  
J. Wang ◽  
Z. Qian ◽  
S. Liu
Keyword(s):  
Residual Stress ◽  
Finite Element ◽  
Stress Field ◽  
Flip Chip ◽  
Residual Stress Field ◽  
Element Analysis ◽  
Sequential Processing ◽  
The Finite Element Analysis ◽  
Flip Chip Packaging ◽  
The Given

In this paper, a nonlinear finite element framework was established for processing mechanics modeling of flip-chip packaging assemblies and relevant layered manufacturing. In particular, topological change was considered in order to model the sequential steps during the flip-chip assembly. Geometric and material nonlinearity, which includes the viscoelastic properties of underfill and the viscoplastic properties of solder alloys, were considered. Different stress-free temperatures for different elements in the same model were used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. As comparison, two FEM models (processing model and nonprocessing model) of the flip-chip package considered, associated with different processing schemes, were analyzed. From the finite element analysis, it is found that the stresses and deflections obtained from nonprocessing model are generally smaller than those obtained from the processing model due to the negligence of the bonding process-induced residual stresses and warpage. The stress values at the given point obtained from the processing model are about 20 percent higher than those obtained from the nonprocessing model. The deflection values at the given points obtained from the processing model are usually 25 percent higher than those obtained from the nonprocessing model. Therefore, a bigger error may be caused by using nonprocessing model in the analysis of process-induced residual stress field and warpage in the packaging assemblies.

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