Effects of Thermal Aging and Au Addition on the Electrical Resistance of Solder Balls in Flip Chip and Ultra-CSP Packages

2003 ◽  
Author(s):  
Xingjia Huang ◽  
S. W. Ricky Lee ◽  
Ming Li ◽  
William Chen
Keyword(s):  
Aging Time ◽  
Microstructural Evolution ◽  
Thermal Aging ◽  
Electrical Resistance ◽  
Flip Chip ◽  
Solder Bumps ◽  
Aging Test ◽  
Solder Balls

The present study is aimed at investigating the effects of thermal aging and Au addition on the electrical resistance of solder balls (bumps) in flip chip (FC) and UltraCSP packages. The specimens include one FC with eutectic Sn-Ag-Cu solder bumps and two types of UltraCSP, which have 20-mil and 30-mil eutectic Sn-Pb solder balls, respectively. The thermal aging test is performed with thermal aging at 175°C for FC, and 150°C for CSPs for up to 2000 hours, respectively. The electrical resistance of each daisy-chain pair of solder balls is measured using the Four Point Kelvin Method. With the increase in thermal aging time, electrical resistance of CSPs without Au increases gradually. After 1000 hour, the resistance seems to level off. While the resistance of CSPs with Au addition ascends monotonically with prolonged thermal aging. For Sn-Ag-Cu flip chip solder bumps, at 175°C for only 24 hours, the electrical resistance of a daisy-chain pair of solder bumps drops substantially. From 24 to 2000 hours, the electrical resistance increases at first and soon becomes stable. The change in the electrical resistance is related to the microstructural evolution in the solder balls.

Electrical resistance of Sn–Ag–Cu ball grid array packages with Sn–Zn–Bi addition jointed at 240 °C

2007 ◽  
Vol 22 (1) ◽  
pp. 113-123
Author(s):  
Po-Cheng Shih ◽  
Kwang-Lung Lin
Keyword(s):  
Control System ◽  
Intermetallic Compound ◽  
Aging Time ◽  
Electrical Resistance ◽  
Ball Grid Array ◽  
Solder Paste ◽  
Solder Balls ◽  
Solder Bulk ◽  
Ball Grid Array Packages

Sn–8Zn–3Bi solder paste and Sn–3.2Ag–0.5Cu solder balls were reflowed simultaneously at 240 °C on Cu/Ni/Au metallized ball grid array substrates. The joints without Sn–Zn–Bi addition (only Sn–Ag–Cu) were studied as a control system. Electrical resistance was measured after multiple reflows and aging. The electrical resistance of the joint (R1) consisted of three parts: the solder bulk (Rsolder bulk, upper solder highly beyond the mask), interfacial solder/intermetallic compound (Rsolder/IMC), and the substrate (Rsubstrate). R1 increased with reflows and aging time. Rsolder/IMC, rather than Rsolder bulk and Rsubstrate, seemed to increase with reflows and aging time. The increase of R1 was ascribed to the Rsolder/IMC rises. Rsubstrate was the major contribution to R1. However Rsolder/IMC dominated the increase of R1 with reflows and aging. R1 of Sn–Zn–Bi/Sn–Ag–Cu samples were higher than that of Sn–Ag–Cu samples in various tests.

Effects of electromigration on microstructural evolution of eutectic SnPb flip chip solder bumps

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2391-2395 ◽  
Author(s):  
Dae-Gon Kim ◽  
Won-Chul Moon ◽  
Seung-Boo Jung
Keyword(s):  
Microstructural Evolution ◽  
Flip Chip ◽  
Solder Bumps ◽  
Eutectic Snpb

Effect of microstructural evolution on electrical property of the Sn–Ag–Cu solder balls joined with Sn–Zn–Bi paste

2005 ◽  
Vol 20 (10) ◽  
pp. 2854-2865 ◽  
Author(s):  
Po-Cheng Shih ◽  
Kwang-Lung Lin
Keyword(s):  
Heat Treatment ◽  
Electrical Property ◽  
Microstructural Evolution ◽  
Electrical Resistance ◽  
Ball Grid Array ◽  
Solder Paste ◽  
Testing Conditions ◽  
Average Resistance ◽  
Solder Balls ◽  
Testing Condition

Sn–8Zn–3Bi solder paste and Sn–3.2Ag–0.5Cu solder balls were reflowed simultaneously on Cu/Ni/Au metallized ball grid array (BGA) substrates. The correlation between microstructural evolution and the electrical resistance of the joints under various testing conditions of reflow cycles and heat treatment was investigated. The electrical resistance of the Sn–Ag–Cu joints without Sn–Zn–Bi was also conducted for comparison. The average resistance values of Sn–Ag–Cu and Sn–Ag–Cu/Sn–Zn–Bi samples changed, respectively, from 7.1 (single reflow) to 7.3 (10 cycles) mΩ and from 7.2 (single reflow) to 7.6 (10 cycles) mΩ. Furthermore, the average resistance values of Sn–Ag–Cu and Sn–Ag–Cu/Sn–Zn–Bi samples changed, respectively, from 7.1 (aging 0 h) to 7.8 (aging 1000 h) mΩ and from 7.2 (aging 0 h) to 7.9 (aging 1000 h) mΩ. It was also noticeable that the average resistance values of Sn–Ag–Cu/Sn–Zn–Bi samples were higher than those of Sn–Ag–Cu samples in each specified testing condition. The possible reasons for the greater resistance exhibited by the Sn–Zn–Bi incorporated joints were discussed.

Evaluation of electromigration in flip-chip solder joints

2011 ◽  
Vol 2011 (1) ◽  
pp. 000979-000984 ◽  
Author(s):  
Hyun-Kyu Lee ◽  
Yong-Chul Chu ◽  
Myung-Ho Chun ◽  
Sang-Ho Jeon ◽  
Jung-Ug Kwak ◽  
...  
Keyword(s):  
Electric Current ◽  
Flip Chip ◽  
Solder Joints ◽  
Cathode Side ◽  
Time To Failure ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Balls ◽  
Initial Resistance ◽  
Reliability Issue

The flip-chip solder joint has become one of the most important technologies of high-density packaging in the microelectronics industry. But, electromigration has become a critical reliability issue in flip-chip technology. Because the dimensions of solder joints are expected to decrease and current density is expected to increase. This study is about electromigration of flip-chip solder joints, we evaluated many kinds of solder balls such as SnAgCu, SnCu and so on in flip chip package. The lifetime against electromigration was defined the fail from the value of resistance with electric current reaches 1.5 times of that of initial resistance with electric current for. In solder bumps with electric current, since the atoms composed of the solder bump and UBM move in the direction of electron flows, the IMC was accumulated on the anode side. Meanwhile, the IMC disappeared in the cathode side, and the voids were formed. In the solder bumps without electric current, the IMC gradually grew on both sides. SnAgCu had better lifetime than SnCu, and different time-to-failure caused by different crystallographic orientation of Sn. And various dopants in SnCu had a different EM lifetime each other.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

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