A Novel Approach to Optimizing Solder Reflow Process in Assembling PQFN Packages

2009 ◽  
Author(s):  
Youmin Yu ◽  
Y. Q. Su ◽  
S. A. Yao ◽  
Y. W. Jiang ◽  
Sonder Wang
Keyword(s):  
Optimal Transport ◽  
Void Formation ◽  
Present Approach ◽  
Solder Paste ◽  
Trial And Error ◽  
Lead Frame ◽  
Reflow Process ◽  
Novel Approach ◽  
Underlying Principle ◽  
Reliability Performance

Solder void is a common defect during assembling Power Quad Flat No-lead (PQFN) packages. It is detrimental to the packages’ feature of good power management and reliability performance and needs to be controlled within certain specification. Reflow process is well considered as critical to the solder void formation for a given solder paste. The transport index of reflow oven, which determines how solder paste are reflowed through solder reflowing process within the reflow oven, has therefore been optimized by a novel approach in this study. The underlying principle of the optimization is to find such a transport index that solder paste have a best possibility to experience homogeneous heat transfer during reflow phase of the whole reflow process. Different from the traditionally experimental trial and error, the present approach first predicts the optimal transport index by calculating the relative locations of lead frame (solder paste are dispensed on it) to the heating blocks of the reflow oven and the amount of heat input at different locations on the lead frame during the reflow phase. Then only necessary experiments are conducted to validate the prediction. As the theoretic calculations already screen out part of experiments that have to be conducted in the traditional trial and error, the present approach saves time and cost in practice.

Solder Joint Formation Simulation and Component Tombstoning Prediction During Reflow

1998 ◽  
Vol 120 (2) ◽  
pp. 141-144 ◽  
Author(s):  
X. Wu ◽  
X. Dou ◽  
C.-P. Yeh ◽  
K. Waytt
Keyword(s):  
Solder Joint ◽  
Model Simulation ◽  
Software Tool ◽  
Solder Paste ◽  
Reflow Process ◽  
Surface Evolver ◽  
Joint Formation ◽  
Geometry Design ◽  
Reliability Performance ◽  
Public Domain Software

The failure of electrical devices associated with solder joints has become one of the most critical reliability issues for surface-mounted devices. Solder joint reliability performance has been found to be highly dependent on the solder joint configuration, which, in turn, is governed by bond pad size, alloy material, and leadframe structure, as well as solder reflow characteristics. To investigate tombstone effects causing solder joint failure during leadless component reflow process, this work has focused on (1) developing a numerical model for the simulations of the solder joint formation during the reflow process, and (2) determining possibility that a tombstone effect for the leadless component may occur by analyzing the force and torque in the problem. Using this methodology, the tombstone effect associated with different pad geometry configurations and solder paste amount has been analyzed through the application of the public domain software tool Surface Evolver. Simulations show that the tombstoning is very sensitive to pad/component geometry design, solder surface tension, solder paste volume, wetting area, and wetting angle. This model simulation can be used to determine optimal solder paste volume, pad geometry configurations, and solder material for avoiding tombstone effects.

Sequential Reflow-Process Optimization to Reduce Die-Attach Solder Voids

2015 ◽  
Vol 137 (2) ◽  
Author(s):  
Youmin Yu ◽  
Victor Chiriac ◽  
Yingwei Jiang ◽  
Zhijie Wang
Keyword(s):  
Heat Transfer ◽  
Theoretical Prediction ◽  
Integrated Circuit ◽  
Sequential Optimization ◽  
Solder Paste ◽  
Lead Frame ◽  
Reflow Process ◽  
Sequential Method ◽  
Die Attach ◽  
Solder Reflow

Solder voids are detrimental to the thermal, mechanical, and reliability performance of integrated circuit (IC) packages and must be controlled within certain specifications. A sequential method of optimizing solder-reflow process to reduce die-attach solder voids in power quad flat no-lead (QFN) packages is presented. The sequential optimization consists, in turn, of theoretical prediction, heat transfer comparison, and experimental validation. First, the theoretical prediction uses calculations to find the optimal pause location and time for a lead frame strip (with dies bonded to it by solder paste) to receive uniform heat transfer during the solder-reflow stage. Next, reflow profiles at different locations on the lead frame strip are measured. Heat transfer during the reflow stage at these locations is calculated from the measured reflow profiles and is compared to each other to confirm the theoretical prediction. Finally, only a minimal number of actual trials are conducted to verify the predicted and confirmed optimal process. Since the theoretical prediction and heat transfer comparison screens out most of the unnecessary trials which must be conducted in common design of experiment (DoE) and trial-and-error methods, the sequential optimization method saves significant time and cost.

scholarly journals Application of ZnO Nanoparticles in Sn99Ag0.3 Cu0.7-Based Composite Solder Alloys

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1545
Author(s):  
Agata Skwarek ◽  
Olivér Krammer ◽  
Tamás Hurtony ◽  
Przemysław Ptak ◽  
Krzysztof Górecki ◽  
...  
Keyword(s):  
Solder Alloy ◽  
Zno Nanoparticles ◽  
Composite Solder ◽  
Void Formation ◽  
Particle Sizes ◽  
Solder Paste ◽  
Solder Alloys ◽  
Ion Microscopy ◽  
Zno Ceramics ◽  
Thermoelectric Parameters

The properties of Sn99Ag0.3Cu0.7 (SACX0307) solder alloy reinforced with ZnO nanoparticles were investigated. The primary ZnO particle sizes were 50, 100, and 200 nm. They were added to a solder paste at a ratio of 1.0 wt %. The wettability, the void formation, the mechanical strength, and the thermoelectric parameters of the composite solder alloys/joints were investigated. Furthermore, microstructural evaluations were performed using scanning electron and ion microscopy. ZnO nanoparticles decreased the composite solder alloys’ wettability, which yielded increased void formation. Nonetheless, the shear strength and the thermoelectric parameters of the composite solder alloy were the same as those of the SACX0307 reference. This could be explained by the refinement effects of ZnO ceramics both on the Sn grains and on the Ag3Sn and Cu6Sn5 intermetallic grains. This could compensate for the adverse impact of lower wettability. After improving the wettability, using more active fluxes, ZnO composite solder alloys are promising for high-power applications.

Wettability of CNT-Doped Solder under Isothermal Aging

2016 ◽  
Vol 857 ◽  
pp. 76-78
Author(s):  
Norliza Ismail ◽  
Roslina Ismail ◽  
Nur Izni Abd Aziz ◽  
Azman Jalar
Keyword(s):  
Carbon Nanotubes ◽  
Contact Angle ◽  
Isothermal Aging ◽  
Optical Microscope ◽  
Image Analyzer ◽  
Solder Paste ◽  
Reflow Process ◽  
Weight Percentage ◽  
Test Board ◽  
Free Solder

Wettability for lead free solder 99.0Sn-0.3Ag-0.7Cu (SAC237) with addition of different weight percentage carbon nanotube after thermal treatment was investigated. SAC 237 solder powder with flux was mixed with 0.01%, 0.02%, 0.03% and 0.04% carbon nanotubes (CNTs) to form SAC-CNTs solder paste. Printed solder paste on test board with Cu surface finish was then reflow under 270°C temperature and isothermal aging at 150°C for 0,200 and 400 hours. Wettability of SAC-CNT solder was determined by measuring contact angle using optical microscope and image analyzer. As a result, from reflow process right through 400 hours of thermal aging, SAC237 with 0.04% CNT has the lowest contact angle as compared to other SAC-CNTs and SAC237 solder. As a conclusion, addition of carbon nanotubes into solder SAC237 improved their wettability on Cu substrate, especially at 0.04% of CNTs.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

scholarly journals Gaudii: An Automated Graphic Design Expert System

2021 ◽  
Vol 24 (2) ◽  
pp. 1775-1780
Author(s):  
Carlos Glez-Morcillo ◽  
Victor Martin ◽  
David Vallejo Fernandez ◽  
Jose Castro-Schez ◽  
Javier Albusac
Keyword(s):  
Fuzzy Logic ◽  
Expert System ◽  
Evolutionary Computation ◽  
Graphic Design ◽  
Expert Knowledge ◽  
Trial And Error ◽  
Design Elements ◽  
Design Expert ◽  
Novel Approach ◽  
Design Activities

Graphic design is the process of creating graphics to meet specific commercial needs based on knowledge of layout principles and esthetic concepts. This is usually an iterative trial and error process which requires a lot of time even for expert designers. This expert knowledge can be modelled, represented and used by a computer to perform design activities. This paper describes a novel approach named Gaudii (standing for "Intelligent Automated Graphic Design Generator") which utilizes principles and techniques known from the fields of Evolutionary Computation and Fuzzy Logic to automatically obtain design elements. Experimental results that demonstrate the potential of the proposed approach are presented in the area of poster design.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

Effects of nano-copper particles on the properties of Sn58Bi composite solder pastes

2017 ◽  
Vol 34 (1) ◽  
pp. 40-44 ◽  
Author(s):  
Hao Zhang ◽  
Yang Liu ◽  
Fenglian Sun ◽  
Gaofang Ban ◽  
Jiajie Fan
Keyword(s):  
Formation Mechanism ◽  
Composite Solder ◽  
Defect Formation ◽  
Void Formation ◽  
Experimental Results ◽  
Solder Paste ◽  
Content Type ◽  
Weight Percentage ◽  
Copper Particles ◽  
Solder Pastes

Purpose This paper aimed to investigate the effects of nano-copper particles on the melting behaviors, wettability and defect formation mechanism of the Sn58Bi composite solder pastes. Design/methodology/approach In this paper, the mechanical stirring method was used to get the nano-composite solder pastes. Findings Experimental results indicated that the addition of 3 wt.% (weight percentage) 50 nm copper particles showed limited effects on the melting behaviors of the Sn58Bi composite solder paste. The spreading rate of the Sn58Bi composite solder paste showed a decreasing trend with the increase of the weight percentage of 50 nm copper particles from 0 to 3 wt.%. With the addition of copper particles of diameters 50 nm, 500 nm or 6.5 μm into the Sn58Bi solder paste, the porosities of the three types of solder pastes showed a similar trend. The porosity increased with the increase of the weight percentage of copper particles. Based on the experimental results, a model of the void formation mechanism was proposed. During reflow, the copper particles reacted with Sn in the matrix and formed intermetallic compounds, which gathered around the voids produced by the volatilization of flux. The exclusion of the voids was suppressed and eventually led to the formation of defects. Originality/value This study provides an optimized material for the second and third level packaging. A model of the void formation mechanism was proposed.

Thermal Study on High-Power White LED down Light

2011 ◽  
Vol 308-310 ◽  
pp. 2531-2536
Author(s):  
Kun Bai ◽  
Li Gang Wu ◽  
Qiu Hua Nie ◽  
Shi Xun Dai ◽  
Bo You Zhou ◽  
...  
Keyword(s):  
High Power ◽  
Heat Sink ◽  
Optimization Methods ◽  
White Led ◽  
Solder Paste ◽  
Lead Frame ◽  
Experiment Data ◽  
Temperature Field Distribution ◽  
Steady Temperature ◽  
Heat Transfer Theory

An actual packaging structural of high power three-chip white LED lamp is designed. The highest temperature of LED chip is 111.2°C, and the temperature range of heat sink is 72.6°C～73.8°C by finite element method (FEM). The respective temperature of lead frame and heat sink are 76.0°C and 71.0°C, which are measured by the thermocouples experiment. Based on the consistency between simulation results and experiment data, considering the steady temperature distribution of the lamp and heat transfer theory, several optimization methods are proposed. The effects of copper pad dimension, solder paste area and natural convection coefficient on the temperature field distribution are calculated.

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