Liquid Cooling of a Stacked Quad-Core Processor and DRAM Using Laminar Flow in Microchannels

2011 ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Furat F. Afram ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Silicon Oxide ◽  
Hot Spot ◽  
Random Access ◽  
System Size ◽  
Thermal Interface Material ◽  
Liquid Cooling ◽  
Silicon Oxide Layer ◽  
Multicore System

Three dimensional (3D) stacking of the processor and memory components in high computing applications reduces the communication delay in multicore system-on-a-chip (SoCs) owing to reduced system size and shorter interconnects. The shorter interconnection length between the processing and memory components in a multicore system lowers the overall system access latencies and boosts the system performance. However, this 3D integration of the processors and memory exacerbates the reliability and thermal problems due to high thermal resistance of the stacked designs. Liquid cooling is the most promising solution to overcome this thermal problem arising in the 3D multicore systems. In this paper, we provide a 3D simulation model comprising of quad-core processor, dynamic random-access-memory (DRAM), liquid cooled microchannel heat sink and air-cooled heat sink. The thermal resistance offered by the silicon oxide layer and thermal interface material (TIM) has also been taken into account. The model assumes the integration of the thermal as well as electrical vias and considers the modified thermal conductivity of the materials in the stack. The cores of the quad-core processor are identical, have non-uniform power dissipation and are arranged in a symmetric layout. The quad-core layouts are based on the traditional and optimized floor plan of a single-core microprocessor. The paper reports the results for both planar flow and impingement flow in the microchannels. The thermal efficiency of the 3D design is evaluated on the basis of the hot spot temperature, hot spot spread and number of hot spots on the surface of the chip as well as DRAM.

Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias

2013 ◽  
Vol 135 (4) ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Furat F. Afram ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Hot Spot ◽  
Three Dimensional ◽  
Memory Access ◽  
Microchannel Heat Sink ◽  
Multicore System ◽  
Floor Planning ◽  
Microchannel Cooling ◽  
Silicon Vias

The electronics industry is heading toward the three-dimensional (3D) microprocessor to cope with higher computing workloads. The 3D stacking of the processor and the memory components reduces the communication delay in multicore system-on-a-chip (SoCs), owing to reduced system size and shorter interconnects. The shorter interconnects in a multicore system lowers the memory access latencies and contributes to improvements in memory access bandwidth. The shorter interconnects in stacked architectures also enables small drivers for interconnections which further reduce interconnection-level-energy dissipations. On the down side, the 3D-stacked architectures have high thermal resistance, which in conjunction with poor thermal management techniques, poses a thermal threat to the reliability of the device. This paper establishes the significance of the microprocessor floor planning and single-phase microchannel cooling for solving the thermal issues arising in the 3D-stacked-quad-core processor. The 3D-stacked-quad-core processor considered in this study comprises of symmetric nonuniformly powered quad-core processor, liquid-cooled microchannel heat sink, dynamic random access memory (DRAM), thermal interface material (TIM), and heat spreader. The electrical through-silicon-vias (TSVs) between the processor and DRAM serve as interconnects, while the thermal TSVs reduce the internal thermal resistance. The effective cooling of the 3D-stacked-quad-core processor depends on the TSVs, quad-core layout and the optimized design of the microchannel heat sink for the desired coolant. The microchannel cooling of the 3D-stacked processor is done both by planar flow and impingement flow. The thermal efficiency of the cooling techniques is evaluated on the basis of hot spot temperature, hot spot spread, and number of hot spots.

scholarly journals Optimisation of a microelectronic assembly package using response surface methodology

2021 ◽  
Vol 39 (4) ◽  
pp. 1058-1065
Author(s):  
M. Ekpu
Keyword(s):  
Response Surface Methodology ◽  
Thermal Resistance ◽  
Response Surface ◽  
Heat Sink ◽  
Chip Thickness ◽  
Thermal Interface Material ◽  
Resistance Response ◽  
Temperature Solution ◽  
Design Software ◽  
Central Composite

This article addressed heat conduction in microelectronics applications. ANSYS finite element design software was used to design the model, while Design Expert software was used for the response surface methodology (RSM) analysis. The components analysed were heat-sink base (HSB) thickness, thermal interface material (TIM) thickness, and chip thickness. A design of experiment comprising of 15 central composite design (CCD) for the coded levels (low (-) and high (+)) of the factors were generated. Heat flow was applied to the chip while a convective coefficient was applied to the heat-sink. The temperature solution was used to calculate the thermal resistance response for the 15 CCD experimental runs. The results from the RSM study proposed an optimal (minimization analysis) combination of 3.5 mm, 0.04 mm, and 0.75 mm, for HSB thickness, TIM thickness, and chip thickness respectively. While the optimal mean thermal resistance of 0.31052 K/W was achieved from the proposed optimal parameters. Keywords: RSM; CCD; thermal resistance; temperature; microelectronics

Packaging of High Power UV-LED Modules on Ceramic and Aluminum Substrates

2012 ◽  
Vol 2012 (1) ◽  
pp. 000225-000232 ◽  
Author(s):  
Marc Schneider ◽  
Benjamin Leyrer ◽  
Christian Herbold ◽  
Stefan Maikowske
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Input Power ◽  
Thermal Interface Material ◽  
Maximum Temperature ◽  
Thermal Interface ◽  
Uv Led ◽  
Forward Current ◽  
Water Cooler ◽  
Forced Air

An LED module consisting of 98 UV-LEDs with an emission wavelength of 395 nm placed on a ceramic substrate of 211 mm2 is presented. The module is cooled by a forced air heat sink as well as a high performance microstructured water cooler to lower the thermal resistance. For high thermal conductance a liquid metal as the thermal interface material between substrate and heat sink is used. With the forced air heat sink a maximum irradiance of 27.3 W/cm2 at a forward current of 700 mA and 220 W electrical input power was achieved. The microstructured water cooler enabled an almost doubling of the electrical input power (430 W) while maintaining the chip's maximum temperature. For a reduction of the module's thermal resistance a thick film process for aluminum sheet metal substrates was developed. A prototype LED module with 25 UV-LED chips on an area of 54 mm2 achieved a maximum optical power density of 31.6 W/cm2 at a forward current of 900 mA using a forced air heat sink. For an improved cooling of the LED chips a chip-on-heat sink-technology with embedded water cooling channels is developed to eliminate the thermal interface between substrate and heat sink.

Single-Phase Microchannel Cooling for Stacked Single Core Chip and DRAM

2011 ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
Dereje Agonafer
Keyword(s):  
Thermal Resistance ◽  
Thermal Management ◽  
Heat Sink ◽  
Single Phase ◽  
Cooling System ◽  
Three Dimensional ◽  
Form Factors ◽  
Memory Access ◽  
Thermal Interface Material ◽  
Level Energy

The stacking of processing and memory components in a three-dimensional (3D) configuration enables the implementation of processing systems with small form factors. Such stacking shortens the interconnection length between processing and memory components to dramatically lower the memory access latencies, and contributes to significant improvements in the memory access bandwidth. Both of these factors elevate overall system performance to levels that are not realizable with prevailing and other proposed solutions. The shorter interconnection lengths in stacked architectures also enable the use of smaller drivers for the interconnections, which in turn reduces interconnection-level energy dissipations. On the down side, stacking of processing and memory components introduces a significant thermal management challenge that is rooted in the high thermal resistance of stacked designs. This paper examines and evaluates three distinct solutions that address thermal management challenges in a system that stacks DRAM components onto a processing core. We primarily focus on three different configurations of a microchannel-based single-phase liquid cooling system with a traditional air-cooled heat sink. Our evaluations, which are intended to study the limits of each solution, assume a uniform power dissipation model for the processor and accounts for the thermal resistance offered by the thermal interface material (TIM), the interconnect layer, and through-silicon vias (TSVs). The liquid-cooled microchannel heat sink shows more promising results when integrated into the package than when added to the microprocessor package from outside.

Analysis of ZnO Thin Film as Thermal Interface Material for High Power Light Emitting Diode Application

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
S. Shanmugan ◽  
O. Zeng Yin ◽  
P. Anithambigai ◽  
D. Mutharasu
Keyword(s):  
Thin Film ◽  
Thermal Resistance ◽  
Heat Sink ◽  
Light Emitting Diode ◽  
Thermal Interface Material ◽  
Zno Thin Film ◽  
Thermal Interface ◽  
Light Emitting ◽  
Thermal Paste ◽  
Cu Substrates

All solid-state lighting products produce heat which should be removed by use of a heat sink. Since the two mating surfaces of light emitting diode (LED) package and heat sink are not flat, a thermal interface material (TIM) must be applied between them to fill the gaps resulting from their surface roughness and lack of coplanarity. The application of a traditional TIM may squeeze out when pressure is applied to join the surfaces and hence a short circuit may result. To avoid such a problem, a thin solid film based TIM has been suggested. In this study, a zinc oxide (ZnO) thin film was coated on Cu substrates and used as the TIM. The ZnO thin film coated substrates were used as heat sink purposes in this study. The prepared heat sink was tested with 3 W green LED and the observed results were compared with the results of same LED measured at bare and commercial thermal paste coated Cu substrates boundary conditions. The influence of interface material thickness on total thermal resistance (Rth-tot), rise in junction temperature (TJ), and optical properties of LED was analyzed. A noticeable reduction in Rth-tot (5.92 K/W) as well as TJ (ΔTJ = 11.83 °C) was observed for 800 nm ZnO thin film coated Cu substrates boundary conditions when compared with bare and thermal paste coated Cu substrates tested at 700 mA. Change in TJ influenced the thermal resistance of ZnO interface material. Improved lux level and decreased correlated color temperature (CCT) were also observed with ZnO coated Cu substrates.

Influence of Package-Sink Interface Materials on Die Performance and Reliability

2003 ◽  
Author(s):  
Henry H. Jung ◽  
Sai Ankireddi ◽  
Stanley Pecavar ◽  
James Jones
Keyword(s):  
Thermal Resistance ◽  
Hot Spot ◽  
Thermal Interface Material ◽  
Electronic Packages ◽  
Total Thermal Resistance ◽  
Thermal Interface ◽  
Thermal Solution ◽  
Materials Used ◽  
Interface Materials ◽  
Spot Temperature

For high-power electronic packages, it is generally accepted that the package-sink interface materials used in the thermal solution influence hot-spot temperature(s) and junction-to-ambient thermal resistance. In this article we show how these package-exterior materials can noticeably influence across-die temperature gradients also. The numerical results reveal that the across-die thermal gradient can nearly double over a narrow range of conductivities typical of commercially available package-sink interface materials. Results show that the chip hot-spot temperature can be reduced 4 to 7 C by increasing the thermal interface material conductivity from 1 to 3 W/mk. This improvement can reduce the total thermal resistance from chip to ambient.

Free Convection Limits for Pin-Fin Cooling

1998 ◽  
Vol 120 (3) ◽  
pp. 633-640 ◽  
Author(s):  
T. S. Fisher ◽  
K. E. Torrance
Keyword(s):  
Analytical Solution ◽  
Free Convection ◽  
Thermal Resistance ◽  
Heat Sink ◽  
Heat Dissipation ◽  
Inviscid Flow ◽  
System Size ◽  
Total System ◽  
Pin Fin ◽  
Optimal Values

An analytical solution for a system consisting of a pin-fin heat sink and a chimney is presented. The result is applied to problems in which the size of the overall system is constrained. For a given heat dissipation and total system size, optimal values of the pin-fin diameter and heat-sink porosity are observed. The optima occur for systems with and without chimneys. The optimization is used to show that the minimum thermal resistance from a pin-fin heat sink is about two times larger than that of an idealized model based on inviscid flow.

Experimental Investigation of Liquid Cooling Through Shallow Copperclad Cavities With Etched Pin-Fin Arrays

2018 ◽  
Author(s):  
Yin Lam ◽  
Nicole Okamoto ◽  
Younes Shabany ◽  
Sang-Joon John Lee
Keyword(s):  
Pressure Drop ◽  
Thermal Resistance ◽  
Surface Area ◽  
Flow Rate ◽  
Heat Sink ◽  
Heat Removal ◽  
Heat Sinks ◽  
Liquid Cooling ◽  
Pin Fin ◽  
Pin Fin Arrays

Heat removal is an increasing engineering challenge for higher-density packaging of circuit components. Microchannel heat sinks with liquid cooling have been investigated to take advantage of high surface-to-volume ratio and higher heat capacity of liquids relative to gases. This study experimentally investigated heat removal by liquid cooling through shallow copperclad cavities with staggered pin-fin arrays. Cavities with pin-fins were fabricated by chemical etching of a copperclad layer (nominally 105 μm thick) on a printed-circuit substrate (FR-4). The overall etched cavity was 30 mm wide, 40 mm long, and 0.1 mm deep. The pins were 1.1 mm in diameter and were distributed in a staggered arrangement. The cavity was sealed with a second copperclad substrate using an elastomer gasket. This assembly was then connected to a syringe pump delivery system. Deionized water was used as the working fluid, with volumetric flow rate up to 1.5 mL/min. The heat sink was subjected to a uniform heat flux of 5 W on the underside. Performance of the heat sink was evaluated in terms of pressure drop and the convection thermal resistance. Pressure drop across the heat sinks was less than 10 kPa, dominated by wall surface area rather than the small surface area contributed by cylindrical pins. At low flow rate, caloric thermal resistance dominated the overall thermal resistance of the heat sink. When compared to a microchannel without pins, the pin-fin microchannel reduced convective thermal resistance of the heat sink by approximately a factor of 4.

Thermal Resistance Analysis of High Power Light Emitting Diode Using Aluminum Nitride Thin Film-Coated Copper Substrates as Heat Sink

2014 ◽  
Vol 136 (3) ◽  
Author(s):  
S. Shanmugan ◽  
D. Mutharasu
Keyword(s):  
Thin Film ◽  
Aluminum Nitride ◽  
Thermal Resistance ◽  
High Power ◽  
Heat Sink ◽  
Light Emitting Diode ◽  
Thermal Interface Material ◽  
Circuit Board ◽  
Light Emitting ◽  
Cu Substrate

AlN thin film was coated over Cu substrate (575 mm2) with 400 nm thickness using DC sputtering for thermal interface material (TIM) application. Aluminum Nitride (AlN)-coated Cu substrate (AlN/Cu) was used as a heat sink for 3-W green light emitting diode (LED). The thermal transient curve was recorded for given LED attached with bare Cu and AlN-coated Cu substrate at three different driving currents. LED attached on AlN/Cu showed the reduced raise in junction temperature (TJ) by 2.59 °C at 700 mA. The LED/TIM/AlN/Cu boundary condition was not supported to reduce the TJ. The total thermal resistance (Rth-tot) was reduced for AlN-coated Cu substrate at 350 mA. The thermal resistance between metal core printed circuit board and Cu substrate (Rth-b-hs) was also observed as low for AlN-coated Cu substrates compared with other boundary conditions measured at 700 mA. The observed results were supported for the use of AlN thin film as TIM in high power LEDs.

GNPs Reinforced Epoxy Nanocomposites Used as Thermal Interface Materials

2016 ◽  
Vol 38 ◽  
pp. 18-25 ◽  
Author(s):  
A. Jiménez-Suárez ◽  
R. Moriche ◽  
S.G. Prolongo ◽  
M. Sánchez ◽  
A. Ureña
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Contact Resistance ◽  
Heat Sink ◽  
Thermal Interface Material ◽  
Thermal Interface Materials ◽  
Thermal Interface ◽  
Heat Increment ◽  
Interface Materials ◽  
Very High

The current tendency in electronics is the reduction of size while continuously increasing the power consumption due to new functionalities and applications. Both aspects generate a heat increment. Consequently, dissipating the heat to the environment is necessary in order to avoid component overheating. [1,2]. The most efficient way to achieve it is to allow the heat to flow from the hot component to a heat sink. In order to improve the efficiency of this process, thermal resistance between both components must be reduced which is usually done by using a thermal interface material (TIM) between both surfaces [3-5]. This material should fill the gaps created due to the microscopic roughness of both surfaces and it must have good thermal conductivity [6]. These air filled gaps result in a very high contact resistance between joined parts, as the air thermal conductivity is very low [7].

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