Contact Reliability of Innovative Compliant Interconnects for Next Generation Electronic Packaging
The ongoing research work at Georgia Institute of Technology, PARC, Inc., and Nanonexus, Inc. funded by NIST/ATP, aims to develop a novel compliant interconnect technology based on stress-engineering of thin-film metal deposition. The minimum pitch size can reach as small as 6 μm. The fabrication of the stress-engineered compliant interconnect is compatible with the standard IC fabrication processes. Therefore, the compliant interconnect fabrication can be fully integrated into front-end semiconductor process. Also, thousands of interconnects can be fabricated on the wafer in one batch, which can greatly reduce the cost, improve the yield, and facilitate wafer level packaging (WLP). Based on the mechanical advantage of the stress-engineered compliant interconnect, a non-soldering assembly process has been developed. In the non-soldering assembly process, compliant interconnects are pressed against the bonding pads to establish the electrical connection. Test vehicles with such non-soldering contact interconnect have been assembled and subjected to thermal cycling. Although the assembled test vehicles have shown reliability over 1000 cycles, the primary mode of failure occurs at the contact interface between the compliant interconnect tip and the bonding pad. This contact interface is studied using analytical and numerical models to understand the reliability of freestanding sliding-contact compliant interconnect assembly.