Novel Process Techniques to Reduce Voids in Solder Thermal Interface Materials Used for Flip-Chip Package Applications

2005 ◽  
Author(s):  
M. Montano ◽  
J. Garcia ◽  
W. Shi ◽  
M. T. Reiter ◽  
U. Vadakkan ◽  
...  
Keyword(s):  
Process Parameters ◽  
Thermal Performance ◽  
Flip Chip ◽  
Technical Conference ◽  
Thermal Interface Material ◽  
Electronic Systems ◽  
Thermal Interface ◽  
Cure Time ◽  
Materials Used ◽  
The Impact

In the present study, the thermal performance of flip chip electronics packages was evaluated by characterizing the amount of voiding present in the Solder Thermal Interface Material (STIM) which is placed between the die and Integrated Heat Spreader (IHS). The study found that the thermal resistance, Rjc (resistance between the Si die and IHS), is dependent upon the amount of voiding present as well as the location of the voiding in the STIM. The study also described the techniques to reduce the STIM voids in flip chip packages and identified the key process parameters to improve the thermal performance. The process parameters varied in this study consisted of STIM thickness, dwell time and temperature, flux weight, and many others. A detailed DOE and statistical analysis were carried out to determine the impact of the parameters mentioned above toward reducing the quantity of voids in the STIM. The analysis showed that for the packages under consideration, the primary process parameters that affect the STIM voiding are cure time, flux weight and TIM thickness.   This paper was also originally published as part of the Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems.

Finite element analysis of lidded flip-chip packages: A study on the impact of thermal interface material compressibility and stress-free conditions on modeling predictions

2015 ◽  
Vol 2015 (1) ◽  
pp. 000151-000156
Author(s):  
Tuhin Sinha
Keyword(s):  
Flip Chip ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Element Analysis ◽  
Thermal Interface ◽  
Strong Function ◽  
Linear Elastic ◽  
Fea Modeling ◽  
Predicted Values ◽  
The Impact

In this paper, we present the effects of assumptions made about the constitutive behavior of a cured, silicone gel type thermal interface material (TIM) and the package stress-free conditions on FEA modeling predictions. The focus will be on the deformations (or warpage) predicted by the models for lidded flip-chip packages. It is critical for such warpage predictions to be close to experimental measurements for accurate projection of mechanical stresses and strains in a package. Digital Image Correlation (DIC) warpage measurements on flip-chip modules are compared against the predicted values and the impact of above-mentioned assumptions will be discussed. It will be shown that the TIM mechanical and thereby, thermal degradation is a strong function of the TIM compressibility and stress-free condition assumptions. Bounds of non-linear elastic modeling technique for the TIM and guidelines for conducting numerical analysis for lidded flip-chip packages will be provided.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

scholarly journals Use of 1D mechanical and thermal models to predetermine the heat transferable by a thermal interface material layer in space applications

2020 ◽  
Vol 234 (17) ◽  
pp. 3459-3473
Author(s):  
Simon Vandevelde ◽  
Alain Daidié ◽  
Marc Sartor
Keyword(s):  
Heat Transfer ◽  
Thermal Performance ◽  
Thermal Contact ◽  
Interface Layer ◽  
Thermal Interface Material ◽  
Space Applications ◽  
Thermal Interface ◽  
Steady State Heat ◽  
Steady State Heat Transfer ◽  
Assistance Tool

This paper proposes the use of 1D basic models to build a design assistance tool capable of evaluating the heat transfer between a third-level electronic packaging and its support, considering a conventional configuration where a thermal interface material is placed between these two parts. Using this kind of tool early in the design process may facilitate choices concerning geometry and material. The packaging is modelled by a stepped beam (the equipment) and the interface layer by a nonlinear elastic foundation (the thermal interface material). Considering that the electronic equipment bends under the effect of the forces exerted by the fasteners, the tool makes it possible to determine the contact zone remaining operative after deformation, and the pressure distribution at the interface. Mechanical results are then used to calculate the steady-state heat transfer between the equipment and its support, taking into account the diffusion within the equipment and the thermal interface material, and also the thermal contact resistances, the latter being dependent on the contact pressure. A detailed case study is used to illustrate the utility of the approach. The 1D models are exploited to illustrate the interest of the design assistance tool. The influence of different parameters on the thermal performance is studied and a new innovative proposal is analyzed, which could lead to a significant increase in thermal performance.

scholarly journals Reliability Investigation of a Carbon Nanotube Array Thermal Interface Material

Energies ◽  
2019 ◽  
Vol 12 (11) ◽  
pp. 2080 ◽  
Author(s):  
Andreas Nylander ◽  
Josef Hansson ◽  
Majid Kabiri Samani ◽  
Christian Chandra Darmawan ◽  
Ana Borta Boyon ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Thermal Performance ◽  
Photoelectron Spectroscopy ◽  
Thermal Contact ◽  
Thermal Interface Material ◽  
Thermal Interface Materials ◽  
Thermal Interface ◽  
Thermal Interface Resistance ◽  
Further Development ◽  
Interface Materials

As feature density increases within microelectronics, so does the dissipated power density, which puts an increased demand on thermal management. Thermal interface materials (TIMs) are used at the interface between contacting surfaces to reduce the thermal resistance, and is a critical component within many electronics systems. Arrays of carbon nanotubes (CNTs) have gained significant interest for application as TIMs, due to the high thermal conductivity, no internal thermal contact resistances and an excellent conformability. While studies show excellent thermal performance, there has to date been no investigation into the reliability of CNT array TIMs. In this study, CNT array TIMs bonded with polymer to close a Si-Cu interface were subjected to thermal cycling. Thermal interface resistance measurements showed a large degradation of the thermal performance of the interface within the first 100 cycles. More detailed thermal investigation of the interface components showed that the connection between CNTs and catalyst substrate degrades during thermal cycling even in the absence of thermal expansion mismatch, and the nature of this degradation was further analyzed using X-ray photoelectron spectroscopy. This study indicates that the reliability will be an important consideration for further development and commercialization of CNT array TIMs.

Precise, high throughput dispensing of thermal interface material in BGA packaging applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001391-001412
Author(s):  
Hanzhuang Liang ◽  
Linh Rolland
Keyword(s):  
High Throughput ◽  
Flip Chip ◽  
Consumer Electronics ◽  
Thermal Interface Material ◽  
Production Lines ◽  
Heat Spreader ◽  
Heavy Load ◽  
Thermal Interface ◽  
Wide Range ◽  
Complicated Geometries

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

Measuring and Optimizing Thermal Interface Material Performance for VR Heatsink Designs

2015 ◽  
Author(s):  
Jun Lu ◽  
Michelle C. Lin ◽  
Bernie Short
Keyword(s):  
Thermal Performance ◽  
Mechanical Test ◽  
Thermal Interface Material ◽  
Thermal Testing ◽  
Performance Measurements ◽  
Thermal Interface ◽  
Test Board ◽  
And Performance ◽  
The Right ◽  
The Given

With increasingly high powers on processors, memories, and chipsets, the voltage regulators (VR) become heavily loaded and a heatsink is often required to prevent overheating the surrounding components on the board. For VR heatsink designs, thermal interface silicone gap filler pads are often used and there is an increasing need to improve VR thermal solutions by reducing thermal resistance of the TIM. A series of TIM2 thickness and performance measurements based on thermal testing was performed in order to understand gap filler characteristics, optimize TIM performance, and utilize best retention design. By utilizing a VR thermal and mechanical test board in wind tunnel testing using the same VR heatsink, thermal performance of TIM2 using gap filler pads over a range of airflow velocities can be measured and compared. The study shows how the optimum TIM performance can be achieved by using the gap filler pads with appropriate thickness for the given designed heatsink standoff heights. The benefit of choosing the right thickness pads over others can be significant and is a valuable learning that can be applied to future VR heatsink designs. Furthermore, the silicone gap filler characteristics and its relationship to board bending and result TIM thickness and thermal performance are investigated and further improved. The learnings help understand the limitations and where the area of improvement can be for future VR heatsink designs.

Design, Synthesis, and Performance of a Carbon Nanotube/Metal Foil Thermal Interface Material

2007 ◽  
Author(s):  
Baratunde A. Cola ◽  
Xianfan Xu ◽  
Timothy S. Fisher
Keyword(s):  
Carbon Nanotube ◽  
Thermal Performance ◽  
Thermal Conduction ◽  
Thermal Interface Material ◽  
Metal Foil ◽  
Thermal Interface ◽  
Design Synthesis ◽  
Cnt Arrays ◽  
And Performance ◽  
Contact Spots

The thermal performance of an interface material comprised of a metal foil with dense, vertically oriented carbon nanotube (CNT) arrays synthesized on both of its surfaces is characterized for rough and smooth interfaces. The CNT/foil deforms in the interfaces by two mechanisms, CNT deformation and foil deformation, that may significantly increase the number of CNT contact spots on both sides of the foil. As a result, the thermal conduction at the CNT-array-free-tip interfaces is greatly increased from previous measurements.

Sign in / Sign up

Export Citation Format

Share Document