The Effects of Nonlinearity on Parametric Amplifiers

2008 ◽  
Author(s):  
Jeffrey F. Rhoads ◽  
Steven W. Shaw
Keyword(s):  
Performance Metrics ◽  
Dynamic Range ◽  
Noise Signal ◽  
Low Noise ◽  
Nonlinear Frequency ◽  
Parametric Amplifiers ◽  
Lumped Mass ◽  
Mass Model ◽  
Nonlinear Frequency Response ◽  
On Chip

Mechanical and electromechanical parametric amplifiers have garnered significant interest, as of late, due to the increased need for low-noise signal amplification in resonant micro/nanosystems. While these devices, which are traditionally designed to operate in a linear range, potentially represent an elegant, on-chip amplification solution, it is not readily apparent that this technical approach will suffice in all micro/nanoresonator implementations, due to the scale-dependent nature of a mechanical or electromechanical amplifier’s dynamic range. The present work investigates whether the aforementioned linear dynamic range constraint is truly a practical limitation, by considering the behavior of a representative degenerate parametric amplifier driven within a nonlinear frequency response regime. The work adopts a comparatively simple lumped-mass model for analysis and proceeds with the characterization of pertinent performance metrics, including gain/pump and gain/phase behaviors. Ultimately, the work concludes that parametric amplification can be realized in a nonlinear context, but such implementations generally lead to inferior amplifier performance.

A low-noise and flexible FPGA-based binary signal measurement generator

2019 ◽  
Vol 11 (5-6) ◽  
pp. 447-455 ◽  
Author(s):  
Gordon Notzon ◽  
Robert Storch ◽  
Thomas Musch ◽  
Michael Vogt
Keyword(s):  
Dynamic Range ◽  
Time Lag ◽  
Impulse Response Function ◽  
High Dynamic Range ◽  
Noise Signal ◽  
Low Noise ◽  
Ultra Wideband ◽  
Coded Excitation ◽  
Field Programmable ◽  
Noise Measurements

AbstractIn the area of electromagnetic metrology, binary coded excitation signals become more and more important and various binary coded sequences are available. The measurement approach is to assess the impulse response function of a device under test by correlating the response signal with the excitation signal. In order to achieve a high measurement reproducibility as well as a high dynamic range, the generated binary coded signals have to provide low-noise. In this contribution, a low-noise signal generator realized with a field programmable gate array is presented. The performance investigation of different kinds of binary coded excitation signals and different correlation concepts have been practically investigated. With a chip rate of 5 Gchip/s, the generator can be utilized for ultra-wideband applications. In order to allow for a low-noise and long-term stable signal generation, a new clock generator concept is presented and results of phase noise measurements are shown. Furthermore, an algorithm to fast and precisely shifting the time lag between two binary coded signals for correlating excitation and response signals with a hardware correlator is presented. Finally, the realized demonstrator system is tested using two commonly used types of binary coded sequences.

A Study of Noise Impact on the Stability of Electrostatic MEMS

2020 ◽  
Vol 15 (11) ◽  
Author(s):  
Yan Qiao ◽  
Wei Xu ◽  
Hongxia Zhang ◽  
Qin Guo ◽  
Eihab Abdel-Rahman
Keyword(s):  
Noise Intensity ◽  
Initial Conditions ◽  
Basins Of Attraction ◽  
Low Noise ◽  
Intensity Level ◽  
Lumped Mass ◽  
Mass Model ◽  
Restoring Force ◽  
Electrostatic Mems ◽  
The Stability

Abstract Noise-induced motions are a significant source of uncertainty in the response of micro-electromechanical systems (MEMS). This is particularly the case for electrostatic MEMS where electrical and mechanical sources contribute to noise and can result in sudden and drastic loss of stability. This paper investigates the effects of noise processes on the stability of electrostatic MEMS via a lumped-mass model that accounts for uncertainty in mass, mechanical restoring force, bias voltage, and AC voltage amplitude. We evaluated the stationary probability density function (PDF) of the resonator response and its basins of attraction in the presence noise and compared them to that those obtained under deterministic excitations only. We found that the presence of noise was most significant in the vicinity of resonance. Even low noise intensity levels caused stochastic jumps between co-existing orbits away from bifurcation points. Moderate noise intensity levels were found to destroy the basins of attraction of the larger orbits. Higher noise intensity levels were found to destroy the basins of attraction of smaller orbits, dominate the dynamic response, and occasionally lead to pull-in. The probabilities of pull-in of the resonator under different noise intensity level are calculated, which are sensitive to the initial conditions.

scholarly journals 22nm FINFET Based High Gain Wide Band Differential Amplifier

2021 ◽  
Vol 15 ◽  
pp. 55-62
Author(s):  
G Vasudeva ◽  
Uma B. V.
Keyword(s):  
Performance Metrics ◽  
Dynamic Range ◽  
High Gain ◽  
Low Noise ◽  
Vlsi Circuits ◽  
Differential Amplifier ◽  
Model Parameters ◽  
Front End ◽  
Analog Front End ◽  
High K

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

Axially Modulated Clamped-Guided Arch Resonator for Memory and Logic Applications

2017 ◽  
Author(s):  
Md Abdullah Al Hafiz ◽  
Sherif Tella ◽  
Nouha Alcheikh ◽  
Hossein Fariborzi ◽  
Mohammad I. Younis
Keyword(s):  
Frequency Modulation ◽  
System Integration ◽  
Room Temperature ◽  
Electrostatic Force ◽  
Logic Gate ◽  
Nonlinear Frequency ◽  
Dynamic Memory ◽  
Electrostatically Actuated ◽  
Nonlinear Frequency Response ◽  
On Chip

We experimentally demonstrate memory and logic devices based on an axially modulated clamped-guided arch resonator. The device are electrostatically actuated and capacitively sensed, while the resonance frequency modulation is achieved through an axial electrostatic force from the guided side of the clamped-guided arch microbeam. We present two case studies: first, a dynamic memory based on the nonlinear frequency response of the resonator, and second, a reprogrammable two-input logic gate based on the linear frequency modulation of the resonator. These devices show energy cost per memory/logic operation in pJ, are fully compatible with CMOS fabrication processes, have the potential for on-chip system integration, and operate at room temperature.

Design of Precise DC Millivolt Signal Source Based on System-on-Chip of C8051F410

2011 ◽  
Vol 382 ◽  
pp. 183-186 ◽  
Author(s):  
Ying Wang ◽  
Xue Zhong Ai ◽  
Qi Liu ◽  
Ren Yu Liu
Keyword(s):  
Noise Signal ◽  
Low Noise ◽  
System On Chip ◽  
Signal Source ◽  
Current Output ◽  
Type D ◽  
Power Supply Circuit ◽  
On Chip ◽  
Low Drift ◽  
Analog Output

This paper describes design process of thermocouple signal precise source. System-on-chip of C8051F410 is a key to signal source. It can realize 15 bit analog output through internal two-path 12 bit current output type D/A .Signal amplification circuit includes power supply circuit, low drift, low noise signal that can be verification source of thermocouple measuring instrument.

A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

2011 ◽  
Vol E94-C (10) ◽  
pp. 1698-1701
Author(s):  
Yang SUN ◽  
Chang-Jin JEONG ◽  
In-Young LEE ◽  
Sang-Gug LEE
Keyword(s):  
Low Power ◽  
Digital Tv ◽  
Low Noise ◽  
On Chip ◽  
Tracking Filter

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Microarchitectural Characterization on a Mobile Workload

2021 ◽  
Vol 11 (3) ◽  
pp. 1225
Author(s):  
Woohyong Lee ◽  
Jiyoung Lee ◽  
Bo Kyung Park ◽  
R. Young Chul Kim
Keyword(s):  
Performance Monitoring ◽  
Performance Metrics ◽  
Performance Comparison ◽  
Instruction Level Parallelism ◽  
Data Set ◽  
Performance Events ◽  
Hardware Performance Counters ◽  
On Chip ◽  
The Comparative Study ◽  
Level Parallelism

Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely since the hardware profiling features are limited to the public. As a popular mobile performance workload, it is hard to find Geekbench’s microarchitecture characteristics in mobile devices. In this paper, a thorough experimental study of Geekbench performance characterization is reported with detailed performance metrics. This study also identifies mobile system on chip (SoC) microarchitecture impacts, such as the cache subsystem, instruction-level parallelism, and branch performance. After the study, we could understand the bottleneck of workloads, especially in the cache sub-system. This means that the change of data set size directly impacts performance score significantly in some systems and will ruin the fairness of the CPU benchmark. In the experiment, Samsung’s Exynos9820-based platform was used as the tested device with Android Native Development Kit (NDK) built binaries. The Exynos9820 is a superscalar processor capable of dual issuing some instructions. To help performance analysis, we enable the capability to collect performance events with performance monitoring unit (PMU) registers. The PMU is a set of hardware performance counters which are built into microprocessors to store the counts of hardware-related activities. Throughout the experiment, functional and microarchitectural performance profiles were fully studied. This paper describes the details of the mobile performance studies above. In our experiment, the ARM DS5 tool was used for collecting runtime PMU profiles including OS-level performance data. After the comparative study is completed, users will understand more about the mobile architecture behavior, and this will help to evaluate which benchmark is preferable for fair performance comparison.

Study of plate vibrating in fluids having part-through crack at random angles and locations

2021 ◽  
pp. 095440622110127
Author(s):  
Ruqia Ikram ◽  
Asif Israr
Keyword(s):  
Frequency Response ◽  
Multiple Scales ◽  
Peak Amplitude ◽  
Nonlinear Frequency ◽  
Response Curves ◽  
Crack Location ◽  
Cracked Plate ◽  
Nonlinear Frequency Response ◽  
Angle Crack ◽  
Crack Angle

This study presents the vibration characteristics of plate with part-through crack at random angles and locations in fluid. An experimental setup was designed and a series of tests were performed for plates submerged in fluid having cracks at selected angles and locations. However, it was not possible to study these characteristics for all possible crack angles and crack locations throughout the plate dimensions at any fluid level. Therefore, an analytical study is also carried out for plate having horizontal cracks submerged in fluid by adding the influence of crack angle and crack location. The effect of crack angle is incorporated into plate equation by adding bending and twisting moments, and in-plane forces that are applied due to antisymmetric loading, while the influence of crack location is also added in terms of compliance coefficients. Galerkin’s method is applied to get time dependent modal coordinate system. The method of multiple scales is used to find the frequency response and peak amplitude of submerged cracked plate. The analytical model is validated from literature for the horizontally cracked plate submerged in fluid as according to the best of the authors’ knowledge, literature lacks in results for plate with crack at random angle and location in the presence of fluid following validation with experimental results. The combined effect of crack angle, crack location and fluid on the natural frequencies and peak amplitude are investigated in detail. Phenomenon of bending hardening or softening is also observed for different boundary conditions using nonlinear frequency response curves.

Sign in / Sign up

Export Citation Format

Share Document