Fatigue Testing of Copper Nanoparticle Based Joints and Bonds

2021 ◽  
Author(s):  
Rajesh Sivasubramony ◽  
Maan Z. Kokash ◽  
Sanoop Thekkut ◽  
Ninand Shahane ◽  
Patrick Thompson ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Maximum Temperature ◽  
Nano Particle ◽  
Test Results ◽  
Fine Pitch ◽  
Effects Of Aging ◽  
Sintered Ag

Abstract Fused or sintered Cu nanoparticle structures are potential alternatives to solder for ultra-fine pitch flip chip assembly and to sintered Ag for heat sink attach in high temperature microelectronics. Meaningful testing and interpretation of test results in terms of what to expect under realistic use conditions do, however, require a mechanistic picture of degradation and damage mechanisms. As far as fatigue goes, such a picture is starting to emerge. The porosity of sintered nano-particle structures significantly affects their behavior in cycling. The very different sensitivities to parameters, compared to solder, means new protocols will be required for the assessment of reliability. The present study focused on fatigue in both isothermal and thermal cycling. During the latter, all damage occurs at the low temperature extreme, so life is particularly sensitive to the minimum temperature and any dwell there. Variations in the maximum temperature up to 125 °C did not affect, but a maximum temperature of 200 °C led to much faster damage. Depending on particle size and sintering conditions deformation and damage properties may also degrade rapidly over time. Our picture allows for recommendations as to more relevant test protocols for vibration, thermal cycling, and combinations of these, including effects of aging, as well as for generalization of test results and comparisons in terms of anticipated behavior under realistic long-term use conditions. Also, the fatigue life seems to vary with the ultimate strength, meaning that simple strength testing becomes a convenient reference in materials and process optimization.

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects

2010 ◽  
Vol 2010 (1) ◽  
pp. 000298-000305
Author(s):  
Tae-Kyu Lee ◽  
Weidong Xie ◽  
Thomas R. Bieler ◽  
Kuo-Chuan Liu ◽  
Jie Xue
Keyword(s):  
Thermal Cycling ◽  
Microstructure Evolution ◽  
Isothermal Aging ◽  
Substrate Surface ◽  
Solder Interconnects ◽  
Surface Finishes ◽  
Bga Packages ◽  
Fine Pitch ◽  
Solder Balls

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.

Crack Propagation Versus Crack Initiation Lives of FPSO Weld Details

2010 ◽  
Author(s):  
Inge Lotsberg ◽  
Mamdouh M. Salama
Keyword(s):  
Crack Initiation ◽  
Crack Propagation ◽  
Fatigue Testing ◽  
Fatigue Cracks ◽  
Full Scale ◽  
Test Results ◽  
Inspection Strategy ◽  
Scale Test ◽  
Crack Initiation Life

Documentation of a long crack propagation phase is important for planning a sound inspection program for fatigue cracks in FPSOs. Test results of full scale FPSO weld details have shown that fatigue lives of FPSO details are governed by crack propagation and that crack propagation lives are several times that of the crack initiation life. However, some analysis packages predict a short crack propagation life until failure compared to the crack initiation life. These predictions are not consistent with full scale test results and thus cannot be relied on in developing inspection strategy. The reason for this inconsistency in analysis as compared with test results may be due to limitations in the analysis program packages. The paper presents analysis of fatigue testing data on several full scale FPSO weld details. The paper also discusses the effect of “shake-down’ that is not simulated in the full scale constant amplitude testing and would even lead to longer crack propagation lives under the actual long term loading on FPSOs.

Practical Evaluation of PTFE Thermal Behavior Using the Hot Blowout Thermal Cycling Test

2012 ◽  
Author(s):  
Anita R. Bausman ◽  
A. Fitzgerald (Jerry) Waterland
Keyword(s):  
Thermal Cycling ◽  
Compressive Load ◽  
Temperature Limit ◽  
Cycling Performance ◽  
Current Status ◽  
Test Results ◽  
Sealing Performance ◽  
Practical Evaluation ◽  
Bolted Flange

Differential thermal expansion between polytetrafluoroethylene (PTFE) gasket materials and metallic flange/bolt systems, combined with thermally influenced creep relaxation characteristics of all PTFEs, creates limitations in the ability of some PTFE gasket materials to provide long term, reliable sealing performance in process or thermal cycling applications. ASTM F-36 gasket recovery data is sometimes used to assess a gasket’s thermal cycling capabilities; however, it is a poor means of establishing suitability for cycling performance as it is a short duration, ambient temperature test that measures recovery, or springback, of the gasket after the compressive load has been completely released. In order to provide a direct qualification of thermal cycling performance and capabilities, the Hot Blowout Thermal Cycling (HOBTC) test was developed under the guidance of the PVRC (Pressure Vessel Research Council)Bolted Flange Connection Committee as part of the 1995 PTFE Gasket Protocol. The HOBTC test results provide a practically applicable temperature limit under which the tested material, typically a PTFE, can operate safely. In addition, test data reported graphically provide additional insight about the long term behavior of the PTFE material. This paper reviews the current status of the HOBTC test, in the process of being made into an ASTM standard, and practical application of test results to achieve reliable gasket performance.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Flip Chip Joining with Quaternary Low Melting Temperature Solder Bump Fabricated with Injection Molded Solder

2019 ◽  
Vol 2019 (1) ◽  
pp. 000103-000109 ◽  
Author(s):  
Takashi Hisada ◽  
Toyohiro Aoki ◽  
Eiji Nakamura ◽  
Sayuri Kohara ◽  
Hiroyuki Mori
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Quaternary Alloy ◽  
Thermal Cycling Test ◽  
Sac305 Solder ◽  
Cycling Test ◽  
Fine Pitch ◽  
Alloy Solder ◽  
Injection Molded

Abstract IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.

Parents' long-term adjustment to the genetic test results of minors at risk for Long QT Syndrome

2004 ◽  
Author(s):  
K. S. W. H. Hendriks ◽  
F. J. M. Grosfeld ◽  
A. A. M. Wilde ◽  
J. van den Bout ◽  
I. M. van Langen ◽  
...  
Keyword(s):  
At Risk ◽  
Long Qt Syndrome ◽  
Genetic Test ◽  
Test Results ◽  
Long Qt ◽  
Genetic Test Results ◽  
Qt Syndrome

Spray Cooling for Time Resolved Emission Measurements of ICs

2004 ◽  
Author(s):  
Rama R. Goruganthu ◽  
David Bethke ◽  
Shawn McBride ◽  
Tom Crawford ◽  
Jonathan Frank ◽  
...  
Keyword(s):  
Heat Flux ◽  
Thermal Performance ◽  
Flip Chip ◽  
Cooling System ◽  
Spray Cooling ◽  
Junction Temperature ◽  
Maximum Temperature ◽  
Uniform Heat Flux ◽  
High Heat Flux ◽  
Time Resolved

Abstract Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant

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