Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-layered Stacked-chip Packaging

2021 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Shu Kao ◽  
Hou-Chun Liu ◽  
Chia-Ping Hsieh ◽  
Tao-Chih Chang
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Chip Thickness ◽  
Temperature Cycling ◽  
Nonlinear Material ◽  
Element Analysis ◽  
Fatigue Lifetime ◽  
Joint Reliability ◽  
Packaging Structure ◽  
Ic Package

Abstract To overcome the limited operational speed for nano-scaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is the 3D-IC package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of micro solder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg micro solder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg micro solder joint can be achieved at 10 µm of each chip thickness, 230 and 5 µm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermo-mechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

2005 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Prediction Technique ◽  
Packaging Structure

For the purpose of enhancing the solder joint reliability of a wafer level chip scaling package (WLCSP), the WLCSP adopted the familiar design structure where both the stress compliant layer with low elastic modulus and the dummy solder joints are considered as structural supports. However, the predicted fatigue life of the solder joints at the internal part of the packaging structure using the conventional procedures of finite element simulation are higher than under actual conditions as a result of the perfect bonding assumption in the modeling. In this research, in order to improve the thermo-mechanical reliability of the solder joints, a node tie-release crack prediction technique, based on non-linear finite element analysis (FEA), is developed and compared with the estimation of the solder joint reliability using conventional methodology. The predicted results of reliability, using the novel prediction technique, show a lower fatigue life of the solder joint than that when using conventional one when the fracture regions in the dummy solder joints are simulated under quasi-steady state. At the same time, the result of the thermal cycling test also shows good agreement with the simulated result when using the proposed node tie-release crack prediction analysis.

Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

A Comparative Study of the Solder Joint Reliability in Flip Chip Assemblies with Compliant and Rigid Substrates

2007 ◽  
Vol 353-358 ◽  
pp. 2932-2935
Author(s):  
Yong Cheng Lin ◽  
Xu Chen ◽  
Xing Shen Liu ◽  
Guo Quan Lu
Keyword(s):  
Solder Joint ◽  
Fatigue Failure ◽  
Flip Chip ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Failure Behavior ◽  
Stress Strain ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Failure Life

The reliability of solder joints in flip chip assemblies with both compliant (flex) and rigid (PCB) substrates was studied by accelerated temperature cycling tests and finite element modeling (FEM). In-process electrical resistance measurements and nondestructive evaluations were conducted to monitor solder joint failure behavior, hence the fatigue failure life. Meanwhile, the predicted fatigue failure life of solder joints was obtained by Darveaux’s crack initiation and growth models. It can be concluded that the solder joints in flip chip on flex assembly (FCOF) have longer fatigue life than those in flip chip on rigid board assembly (FCOB); the maximum von Mises stress/strain and the maximum shear stress/strain of FCOB solder joints are much higher than those of FCOF solder joints; the thermal strain and stress in solder joints is reduced by flex buckling or bending and flex substrate could dissipate energy that otherwise would be absorbed by solder joint. Therefore, the substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.

Solder Joint Interconnections in Automotive Electronics: Design-for-Reliability and Accelerated Testing

2019 ◽  
Vol 2019 (1) ◽  
pp. 000063-000077
Author(s):  
E. Suhir ◽  
S. Yi ◽  
J. Nicolics
Keyword(s):  
Solder Joint ◽  
Thermal Stresses ◽  
Fatigue Cracks ◽  
Temperature Cycling ◽  
Accelerated Testing ◽  
Design Stage ◽  
Automotive Electronics ◽  
Random Vibrations ◽  
Fatigue Lifetime ◽  
Ic Package

Abstract Three practically important reliability-related questions for solder joint interconnections (SJIs) in automotive electronics, and particularly in its actuator and sensor electron devices, are addressed in this analysis:Could inelastic strains in the solder material be avoided by a rational physical design of the IC package, and, if not, could the sizes of the peripheral inelastic strain areas be predicted and minimized? It is clear that the low cycle fatigue lifetime is inversely proportional to the sizes of the inelastic zones and that the material's fatigue lifetime could be improved dramatically, if the induced strains remain within the elastic range. The Palmgren-Miner rule of linear accumulation of damages can be used, instead of Coffin-Manson relationships, in such a situation.Realizing that, because of the inevitable uncertainties, the difference between highly reliable and an insufficiently robust electronic products is “merely” in the levels of their never-zero probabilities of failure, could these probabilities be assessed, and could this be done at the design stage? A possibility of doing that is particularly critical for SJIs, the most vulnerable structural elements in the today's IC package designs. Reliability of an electronic material or a product cannot be assured, if it is not quantified, and, because of the inevitable and critical uncertainties, this should be done on the probabilistic basis.Should SJI accelerated testing based on costly, time- and labor-consuming and, because of temperature dependency of material properties, possibly even misleading temperature cycling, be replaced by a more physically meaningful, less expensive and more trustworthy accelerated test vehicle, and could low-temperature/random-vibrations bias be employed in this capacity? The rationale behind such a question has to do with the facts that the highest thermal stresses take place at the lowest temperature conditions, and that fatigue cracks, whether elastic or inelastic, propagate most rapidly, when the material experiences random vibrations. This technique has been already reduced to practice in an industrial lab two years ago. The objective of the analysis is to shed light, by using analytical (“mathematical”) modeling, rather than widely spread computer simulation, on the mechanical behavior and the underlying physics of failure in the SJI. Future work should focus primarily on experimentations to confirm theoretical findings and recommendations.

Experimental and Analytical Studies of 28-Pin Thin Small Outline Package (TSOP) Solder-Joint Reliability

1992 ◽  
Vol 114 (2) ◽  
pp. 169-176 ◽  
Author(s):  
J. Lau ◽  
S. Golwalkar ◽  
S. Erasmus ◽  
R. Surratt ◽  
P. Boysan
Keyword(s):  
Solder Joints ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Operating Conditions ◽  
Nonlinear Finite Element ◽  
Element Analysis ◽  
Isothermal Fatigue ◽  
Joint Reliability ◽  
Thermal Fatigue Life ◽  
Fatigue Data

The reliability of 0.5 mm pitch, 28-Pin Thin Small Outline Package (TSOP) solder joints has been studied by experimental temperature cycling and a cost-effective 3-D nonlinear finite element analysis. Temperature cycling results have been presented as a Weibull distribution, and an acceleration factor has been established for the failure rate at operating conditions. Thermal fatigue life of the corner solder joints has been estimated based on the calculated plastic strain, Coffin-Manson equation, and isothermal fatigue data on solders. A correlation between the experimental and analytical results has also been made. Furthermore, failure analysis of the solder joints has been performed using Scanning Electron Microscopy (SEM) and an optical method.

Solder Joint Reliability of SnBi Finished TSOPs with Alloy 42 Lead-Frame under Temperature Cycling

2011 ◽  
pp. 74-74-15 ◽  
Author(s):  
Weiqiang Wang ◽  
Michael Osterman ◽  
Diganta Das ◽  
Michael Pecht
Keyword(s):  
Solder Joint ◽  
Temperature Cycling ◽  
Lead Frame ◽  
Solder Joint Reliability ◽  
Joint Reliability

Elevated Stand-Off Heights in Solder Joint Interconnections of Surface Mounted IC Packages Result in Appreciable Stress and Warpage Relief

2018 ◽  
Vol 2018 (1) ◽  
pp. 000534-000542
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
R. Ghaffarian
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Calculated Data ◽  
Ball Grid Array ◽  
Substantial Improvement ◽  
Stress Model ◽  
Solder Material ◽  
The Difference ◽  
Free Solder ◽  
Ic Package

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.

Thermal Fatigue Prediction for Leadless Solder Joint of TFBGA

2006 ◽  
Author(s):  
Chia-Lung Chang ◽  
Tzu-Jen Lin ◽  
Chih-Hao Lai
Keyword(s):  
Energy Density ◽  
Solder Joint ◽  
Creep Strain ◽  
Thermal Fatigue ◽  
Strain Energy Density ◽  
Strain Energy ◽  
Creep Property ◽  
Inelastic Strain ◽  
Temperature Cycling ◽  
Element Analysis

Nonlinear finite element analysis was performed to predict the thermal fatigue for leadless solder joint of TFBGA Package under accelerated TCT (Temperature Cycling Test). The solder joint was subjected to the inelastic strain that was generated during TCT due to the thermal expansion mismatch between the package and PCB. The solder was modeled with elastic-plastic-creep property to simulate the inelastic deformation under TCT. The creep strain rate of solder was described by double power law. The furthest solder away from the package center induced the highest strain during TCT was considered as the critical solder ball to be most likely damaged. The effects of solder meshing on the damage parameters of inelastic strain range, accumulated creep strain and creep strain energy density were compared to assure the accuracy of the simulation. The life prediction equation based on the accumulated creep strain and creep strain energy density proposed by Syed was used to predict the thermal fatigue life in this study. The agreement between the prediction life and experimental mean life is within 25 per cent. The effect of die thickness and material properties of substrate on the life of solder was also discussed.

Solder Joint Reliability of SnBi Finished TSOPs with Alloy 42 Lead-Frame under Temperature Cycling

2010 ◽  
Vol 7 (8) ◽  
pp. 102939
Author(s):  
Weiqiang Wang ◽  
Michael Osterman ◽  
Diganta Das ◽  
Michael Pecht ◽  
S. W. Dean
Keyword(s):  
Solder Joint ◽  
Temperature Cycling ◽  
Lead Frame ◽  
Solder Joint Reliability ◽  
Joint Reliability

scholarly journals Improving the Solder Joint Reliability of a Power Leadframe Package Using Thermomechanical Simulation

2019 ◽  
pp. 1-6
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Heat Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Mold Material ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Thermomechanical Simulation ◽  
Board Level

Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and this is what makes the development of a power package challenging. One of the usual requirements from customers is that there should be no solder joint failure up to 2,000 thermal cycles. This paper presents the thermomechanical simulation of a power leadframe package that was conducted to improve its solder joint reliability. Board level solder joint cycle life was predicted using finite element analysis and the result was validated with actual solder life result from board level reliability evaluation. Since available solder prediction equation was for the characteristic life (63.2% accumulative failure), using the normalized characteristic life was implemented for predicting the number of cycles to first failure of the solder joint connection and the approach showed good agreement with the actual result. Results also indicated that the choice of epoxy mold material and the type of PCB (printed circuit board) have a significant contribution to the solder joint reliability performance.

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