Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations

2016 ◽  
Vol 138 (2) ◽  
Author(s):  
M. Baris Dogruoz
Keyword(s):  
Thermal Conductivity ◽  
Temperature Distribution ◽  
Joule Heating ◽  
Computer Aided Design ◽  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Circuit Board ◽  
System Level ◽  
Cfd Simulations ◽  
Printed Circuit

A printed circuit board (PCB) comprises a solid piece of dielectric material with embedded layers of current carrying metal traces and vias. Geometric features of these metal traces and vias in modern PCBs are highly nonuniform and complicated such that the card level or system level numerical simulations by using the actual trace and via geometries are computationally expensive. The present study investigates the effects of Joule heating in current carrying traces on the temperature distribution of PCBs by conducting one-way and two-way direct current (DC) electric and computational fluid dynamics (CFD) simulations. DC electric field simulations are performed to determine the power map of trace layers which are modeled as planar heat generating sources by using the temperature-dependent electrical conductivity of the metal trace. The power distribution varies with the implemented size and power thresholds. Thermal conductivity map of the PCB is determined by using the electronic computer-aided design (ECAD) images of the individual layers. By using these planar source and thermal conductivity maps, CFD simulations are conducted to determine the resulting temperature distribution on the board. A methodology is developed and applied to a sample, complex PCB, and the generated results are compared with those of the previous studies and conventional models. The computational data show that the temperature distributions over the PCB and its mounted components experience large variations based on the implemented thermal conductivity mapping and the Joule heating modeling technique.

Computational Modeling of Anisotropic Thermal Conductivity and Joule Heating on Printed Circuit Boards

2011 ◽  
Author(s):  
M. Baris Dogruoz ◽  
Gokul Shankaran ◽  
Gregory Pitner ◽  
Manoj Nagulapally
Keyword(s):  
Thermal Conductivity ◽  
Joule Heating ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Dielectric Material ◽  
Circuit Board ◽  
System Level ◽  
Field Equations ◽  
Printed Circuit ◽  
Anisotropic Thermal Conductivity

A printed circuit board (PCB) consists of consecutive layers of dielectric material and current carrying traces and vias. Conducting system level simulations of PCB’s with detailed trace and via geometries is computationally very expensive. In the present study, the effects of the trace and via geometry in the physical model are taken into account by importing the corresponding ECAD data with which locally varying anisotrpoic thermal conductivity on the PCB is determined accordingly. Moreover, the effects of Joule heating in the current carrying traces are included by using a number of planar heat sources representing individual metal trace layers. The powermap on each of these layers is determined by solving the relevant electric field equations where the temperature dependency of the electrical field is also taken into account. The results are presented on a sample PCB and comparisons are made with the previous studies and conventional models. It is demonstrated that temperature values differ substantially depending on the method of Joule heating treatment used.

scholarly journals MODIFICATION OF TOOL FOR MOVING TRACK SEGMENTS IN DELTA DESIGN CAD

2019 ◽  
pp. 130-133
Author(s):  
A. Yu. Gladkevich
Keyword(s):  
Computer Aided Design ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Design System ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Advantages And Disadvantages ◽  
Development Tools ◽  
Aided Design

Describes the process of improving and developing tools in computer‑aided design system Delta Design. Currently, the modern  process of PCB development is quite complex and time‑consuming process. Existing CAD systems make it easier to design a  printed circuit Board model by providing powerful development tools. Along with the increasing complexity of modern printed  circuit boards, the requirements for development tools are also growing, making them constantly improve. Using the example  of  the  Delta  Design  system,  the  process  of  improving  the  tool  for  moving  track  segments  is  described.  The  analysis  of  the  advantages and disadvantages of the existing tool is made, and the decision on the need to develop a new algorithm is justified.  Of the two proposed variants of such an algorithm, the optimal one was chosen in terms of the quality of the result obtained and  the convenience of operation.

Macro and Micro Thermal Model of an Elevated Temperature Dielectric Breakdown in Printed Circuit Boards

1996 ◽  
Author(s):  
R. Stutzman ◽  
S. Sathe ◽  
B. Sammakia
Keyword(s):  
Thermal Model ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Dielectric Breakdown ◽  
Dielectric Material ◽  
High Current Density ◽  
Thermal Modeling ◽  
Circuit Board ◽  
Printed Circuit ◽  
Defect Site

Abstract A computational macro and micro thermal model of a printed circuit board dielectric breakdown due to local and global heating of the laminate material is presented in this paper. On a macro level, under certain conditions, the circuit board temperature can approach the glass transition temperature (Tg) due to electronic surface mounted components dissipating heat to the board surface. Under these conditions interfacial micro cracks or dielectric inhomogeneities can be aggravated to an extent where localized voltage breakdown can occur across copper planes within the board. The micro thermal modeling results demonstrate that even under relatively high defect resistance levels the localized temperature at the defect site can greatly exceed the Tg of the dielectric material resulting in carbonization and eventually catastrophic failure. A temperature profile at the defect site clearly shows the spike in the local temperature due to the low thermal conductivity properties of the dielectric material and the localized high current density. The thermal modeling was performed using Flotherm (trademark of Flomerics Limited) code.

A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000887-000892 ◽  
Author(s):  
Rudi Hechfellner ◽  
Michiel Kruger ◽  
Tewe Heemstra ◽  
Greg Caswell ◽  
Nathan Blattau ◽  
...  
Keyword(s):  
Solder Joint ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Light Emitting Diodes ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Control ◽  
Circuit Board ◽  
System Level ◽  
Light Emitting ◽  
Printed Circuit

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance. The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime. In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models. It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..

Effects of Trace Layers and Joule Heating on the Temperature Distribution of Printed Circuit Boards: A Computational Study

2009 ◽  
Vol 1 (2) ◽  
Author(s):  
M. Baris Dogruoz ◽  
Manoj K. Nagulapally
Keyword(s):  
Joule Heating ◽  
Hot Spots ◽  
Printed Circuit Board ◽  
Computational Study ◽  
Computational Cost ◽  
Circuit Board ◽  
System Level ◽  
Printed Circuit ◽  
System Level Simulation ◽  
Background Mesh

A printed circuit board (PCB) is generally a multilayered board made of dielectric material and several layers of traces and vias. Performing detailed system-level computational fluid dynamics (CFD) simulations of PCBs including meshed trace and via geometries for each of the layers is impractical. In the present approach, the effects of the trace and via geometry are accurately modeled in the physical model by importing electronics computer aided-design data consisting of the trace and via layout of the board and computing locally varying orthotropic conductivity (kx, ky, and kz) on the printed circuit board using a background mesh. The spatially varying orthotropic conductivity is then mapped from the background mesh to the CFD mesh and used in a system-level simulation of the PCB with a minimal increase in the overall computational cost. On the other hand, as PCB component densities increase, the current densities increase thereby leading to regions of hot spots due to Joule heating. Hence, it is essential that the computational heat transfer simulations account for the heating due to the high current carrying traces. In order to accurately model the Joule heating of traces and vias, it is of essence to solve for the conservation of current in each of these traces. In this study, the effects of both trace layer nonhomogeneity and Joule heating are examined on a sample PCB with several components attached to it. The results are then compared with those from the conventional modeling techniques. It is demonstrated that there is considerable difference in the location of the hot spots and temperature values between two different methods.

Computing method of thermal conductivity of heat dissipation vias in printed circuit board and its optimization

Circuit World ◽  
2015 ◽  
Vol 41 (1) ◽  
pp. 14-19 ◽  
Author(s):  
Shuo Xiao ◽  
Yang Zhao ◽  
Yuan Cao ◽  
Haifeng Jiang ◽  
Wenliang Zhu
Keyword(s):  
Thermal Conductivity ◽  
Printed Circuit Boards ◽  
Heat Dissipation ◽  
Printed Circuit Board ◽  
Research Result ◽  
Circuit Board ◽  
Computational Formula ◽  
Filling Material ◽  
Content Type ◽  
Printed Circuit

Purpose – This paper aims to deduce a set of theory computational formula, and optimize and improve the heat conductivity of vias in printed circuit boards of electrical power apparatus. Design/methodology/approach – The authors adopted numerical simulation and experimental measurement to verify the reliability of this formula. Findings – Research result showed that 0.45 mm was the optimal bore diameter of vias; the conductivity had no obvious improvement when filling material was FR4 or Rogers, but if it was filled with texture of high thermal conductivity like soldering tine, the conductivity would improve a lot; the plating thickness of vias had a greater influence on thermal conductivity. Originality/value – Through the theory computational formula, this paper studied the influence of aperture of vias, filled materials and thickness of copper plated on vias on thermal conductivity.

Correlation Between the Strain on the Printed Circuit Board and the Stress in Chips for the Failure Prediction of Passive Components

2005 ◽  
Author(s):  
Dennis Lau ◽  
S. W. Ricky Lee
Keyword(s):  
Stress Analysis ◽  
Printed Circuit Boards ◽  
Load Condition ◽  
Failure Prediction ◽  
Circuit Board ◽  
System Level ◽  
Design Rule ◽  
Passive Components ◽  
Printed Circuit ◽  
Microelectronic Devices

Due to the demand for miniaturization of microelectronic devices, the density of packaging has become higher and higher. Also, the sizes of components have become smaller and smaller. In addition to advanced active components such as chip scale packages (CSPs) and flip chips (FCs), mini sized passive components such as chip capacitors and resistors are also important elements for high density packaging. It is quite common to see dozens up to hundreds of passive components on printed circuit boards (PCBs). Both active and passive components contribute to the function (and also malfunction) of electronic systems. However, the reliability issues of passive components are often overlooked because they are relatively small in size and cheap in cost. In view of the fact that “small components could lead to big problems”, the present study is conducted to evaluate the threat to passive components assembled on PCBs under a specific type of mechanical loading. Because of the nature of mass production, microelectronic devices are always manufactured in a batch mode. It is quite often that several PCBs are linked together during the surface mount assembly process. Even if the PCB is a stand-alone unit, extra peripheral frames or tie bars are needed for tooling and fixture. After the board level assembly, a depaneling process is usually required to singulate individual PCBs or to remove the tooling frames for the system level assembly. Some depaneling processes may be automated with precision control. However, it is not unusual for operators in the factory to perform manual depaneling. During this process, the PCB is subjected to mechanical bending and the curvature of the bent PCB may be big enough to damage small passive components. The present study is intended to establish a model for the failure prediction of passive components under depaneling load condition. Computational stress analysis is performed with a 3D finite element model. The emphasis is placed on finding the correlation between the bending strain on the PCB (which is an index of the local curvature of the bent PCB) and the bending stress in the passive components (which is the reason to crack capacitors/resistors). It is observed that such a relationship can be established. With this model, the cracking of passive components may be predicted under the depaneling load condition. The understanding of this potential threat can be turned into a design rule to avoid mounting passive components in the “high risk” area on the PCB. As a result, the objective of “design for reliability” (DFR) can be achieved. The details of the aforementioned model and the results of stress analysis will be presented in this paper.

scholarly journals Physics of Failure (PoF) Based Lifetime Prediction of Power Electronics at the Printed Circuit Board Level

2021 ◽  
Vol 11 (6) ◽  
pp. 2679
Author(s):  
Andrew Wileman ◽  
Suresh Perinpanayagam ◽  
Sohaib Aslam
Keyword(s):  
Power Electronics ◽  
Computer Aided Design ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Circuit Board ◽  
Mechanical Shock ◽  
Element Analysis ◽  
Physics Of Failure ◽  
Printed Circuit

This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.

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