Parameter Calibrations on MOSFET Stress Sensors

2012 ◽  
Vol 134 (3) ◽  
Author(s):  
Ren-Tzung Tan ◽  
Hsien Chung ◽  
Ben-Je Lwo ◽  
Chun-Pai Tang ◽  
Kun-Fu Tseng
Keyword(s):  
Carrier Mobility ◽  
Oxide Semiconductor ◽  
Experimental Methodology ◽  
Thermomechanical Coupling ◽  
Coupling Coefficients ◽  
Stress Monitoring ◽  
Monitoring Tool ◽  
Sensor Applications ◽  
Stress Sensors ◽  
Different Types

Due to the carrier mobility changes with the mechanical loading and its small size, the MOSFET (metal-oxide-semiconductor field-effective-transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging. In this work, a complete and accurate approach to calibrate the coefficients for both types of MOSFET stress sensors under thermal and mechanical loadings was investigated quantitatively. Through data from different measurement modes on different types of MOSFET, the optimal experimental methodology was next proposed for the sensor applications on packaging stress extraction. The thermomechanical coupling coefficients for the selected experimental mode were finally extracted so that packaging stress measurements with MOSFET under elevated temperature can be performed more accurately.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

scholarly journals An IoT Platform for Epilepsy Monitoring and Supervising

2017 ◽  
Vol 2017 ◽  
pp. 1-18 ◽  
Author(s):  
Paula M. Vergara ◽  
Enrique de la Cal ◽  
José R. Villar ◽  
Víctor M. González ◽  
Javier Sedano
Keyword(s):  
Monitoring Tool ◽  
Design Decisions ◽  
Iot Platform ◽  
Depth Analysis ◽  
The Everyday ◽  
Different Types ◽  
Main Factors ◽  
Partial Implementation ◽  
Epilepsy Monitoring ◽  
Monitoring Platform

Epilepsy is a chronic neurological disorder with several different types of seizures, some of them characterized by involuntary recurrent convulsions, which have a great impact on the everyday life of the patients. Several solutions have been proposed in the literature to detect this type of seizures and to monitor the patient; however, these approaches lack in ergonomic issues and in the suitable integration with the health system. This research makes an in-depth analysis of the main factors that an epileptic detection and monitoring tool should accomplish. Furthermore, we introduce the architecture for a specific epilepsy detection and monitoring platform, fulfilling these factors. Special attention has been given to the part of the system the patient should wear, providing details of this part of the platform. Finally, a partial implementation has been deployed and several tests have been proposed and carried out in order to make some design decisions.

scholarly journals Design and Analysis of Logic Gates using GaN based Double Gate MOSFET (DG-MOS)

2018 ◽  
Vol 17 (1) ◽  
Author(s):  
Md Ibnul Bin Kader Arnub ◽  
M Tanseer Ali
Keyword(s):  
Field Effect Transistors ◽  
Logic Gates ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Channel One ◽  
Turn On ◽  
Double Gate Mosfet ◽  
Different Types

The double gate MOSFET, where two gates are fabricated along the length of the channel one after another. Design of logic gates is one of the most eminent application of Double Gate MOSFET. Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are shown to be promising for digital logic applications. This paper describes the design and analysis of different types of logic gates using GaN based DG-MOSFET. The gate length (LG) is kept constant at 10.6 nm. The gate voltage varies from 0 to 1 V for the device switching from turn OFF to turn ON-state. For the device with HfO2 as gate oxide, the ON-state current (ION) and OFF-state current (IOFF) are found 8.11×10-3 and 6.38605×10-9A/μm respectively. The leakage current is low for the device with HfO2 as compared to that for the device with ZrO2. The subthreshold swing (SS) is 68.7408 mV/dec for the device with HfO2.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

scholarly journals Large thickness dependence of the carrier mobility in a transparent oxide semiconductor, La-doped BaSnO3

2018 ◽  
Vol 112 (23) ◽  
pp. 232102 ◽  
Author(s):  
Anup V. Sanchela ◽  
Mian Wei ◽  
Haruki Zensyo ◽  
Bin Feng ◽  
Joonhyuk Lee ◽  
...  
Keyword(s):  
Carrier Mobility ◽  
Thickness Dependence ◽  
Oxide Semiconductor ◽  
Large Thickness ◽  
Transparent Oxide ◽  
Transparent Oxide Semiconductor ◽  
La Doped

scholarly journals VLSI Architectures for Image Interpolation: A Survey

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
C. John Moses ◽  
D. Selvathi ◽  
V. M. Anne Sophia
Keyword(s):  
Large Scale ◽  
Piecewise Linear ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Interpolation ◽  
Hardware Architecture ◽  
Oxide Semiconductor ◽  
Weighting Coefficient ◽  
Vlsi Architectures ◽  
Different Types ◽  
Memory Buffer

Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient.

Characterization of the Piezoresistive Coefficients of (100) Silicon From −150 to +125C

2007 ◽  
Author(s):  
Chun-Hyung Cho ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling
Keyword(s):  
Integrated Circuit ◽  
Carrier Mobility ◽  
Limited Data ◽  
Experimental Calibration ◽  
Four Point Bending ◽  
Stress Sensors ◽  
Stress Sensing ◽  
Test Chips ◽  
Crystallographic Axes

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.

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