Packaging Architecture Considerations of High Density Multi-Chip Electronic Packages Via System Optimization

1990 ◽  
Vol 112 (3) ◽  
pp. 267-271 ◽  
Author(s):  
J. P. Krusius
Keyword(s):  
System Optimization ◽  
High Density ◽  
Electronic Packages ◽  
Future Trends ◽  
Printed Wiring Board ◽  
Trade Off ◽  
Systematic Methodology ◽  
Cmos Chip ◽  
Wiring Board ◽  
Minimum System

Multi-chip packaging of high density CMOS based systems is analyzed using package system simulation, a new systematic methodology for design and trade-off studies of electronic packages in order to examine future trends. Technology parameters for a representative CMOS chip, multi-chip package (MCP), and printed wiring board technology are defined. Six key MCP parameters are optimized using simulated annealing. A large number of different optimum MCP’s for minimum system cycle time have been found. Based on this set key packaging parameter relationships are derived and associated future trends discussed. Finally, the significance of these trends to mechanical engineers is outlined.

Materials, Mechanical, and Thermal Considerations of High Density Multi-Chip Electronic Packages

1989 ◽  
Vol 167 ◽  
Author(s):  
J. Peter Krusius
Keyword(s):  
Simulated Annealing ◽  
System Simulation ◽  
High Density ◽  
Large Set ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Trade Off ◽  
Systematic Methodology ◽  
Cmos Chip ◽  
Wiring Board

AbstractMulti-chip packages (MCP) are analyzed for high density CMOS packaging using package system simulation, a new systematic methodology for design and trade-off studies of electronic packages. Technology parameters for a representative CMOS chip, multi-chip package, and printed wiring board technology are defined. The effect of these technology parameters on the characteristics of the MCP are examined. The MCP's are optimized using simulated annealing. A large set of optimum MCP's has been found. Based on this set, MCP technology parameters are ranked and their implications on future high density MCP's discussed.

Warpage Measurement Using Projection Moire´ System and Two Automatic Image Segmentation Algorithms

2007 ◽  
Author(s):  
Wei Tan ◽  
I. Charles Ume
Keyword(s):  
Image Segmentation ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Segmentation Algorithms ◽  
Out Of Plane ◽  
Cte Mismatch ◽  
Image Models ◽  
Wiring Board ◽  
Plane Displacement ◽  
Projection Moire

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to serious reliability problems. In this paper, a projection moire´ warpage measurement system and two types of automatic image segmentation algorithms were presented. In order to use the projection moire´ technique to separately determine the warpage of a PWB and assembled electronic packages in a PWBA, two image segmentation algorithms based on mask image models and active contour models (snakes) were developed. They were used to detect package locations in a PWBA displacement image generated by the projection moire´ system. The performances of the mask image and snake approaches based on their resolutions, processing rates, and measurement efficiencies were evaluated in this research. Real-time composite Hermite surface models were constructed to estimate the PWB warpage values underneath the electronic packages. The above automatic image segmentation algorithms were integrated with the projection moire´ system to accurately evaluate the warpage of PWBs and assembled chip packages individually.

Acceleration Factor to relate Thermal Cycles to Power Cycles for Ceramic Ball Grid Area Array Packages

2006 ◽  
Vol 3 (4) ◽  
pp. 177-193 ◽  
Author(s):  
Andy Perkins ◽  
Krishna Tunga ◽  
Suresh Sitaraman
Keyword(s):  
Fatigue Life ◽  
Environmental Parameters ◽  
Acceleration Factor ◽  
Junction Temperature ◽  
Design Parameters ◽  
Substrate Thickness ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Ceramic Ball ◽  
Wiring Board

There is a need for a new Acceleration Factor (AF) that can relate Accelerated Thermal Cycle (ATC) fatigue life to Power Cycle (PC) fatigue life quickly and accurately in order to avoid over designing electronic packages for benign environments. An AF, such as the Norris-Landzberg AF, is only applicable when using it to predict fatigue life within the same environment, i.e. ATC to ATC or PC to PC. This work proposes an AF that takes into account the differences between ATC tests and PC tests for ceramic ball grid array (CBGA) packages by considering relevant design and environmental parameters. The new AF is based on relevant design parameters such as substrate size, substrate thermal conductivity, substrate thickness, coefficient of thermal (CTE) mismatch between the substrate and printed wiring board (PWB), PWB thickness, and environmental parameters such as temperature range (ΔT), frequency of cycles (f), and peak/junction temperature (Tj). Finite Element Models (FEM), experimental data, laser moiré interferometry, Design of Simulation (DOS), ANOVA, and regression analysis are used to develop the new AF. The new AF can be used to more accurately assess PC fatigue life from ATC tests so that expensive over-designing of electronic packages can be avoided for desktop/server/laptop applications.

Extending the Fatigue Life of Solder Grid Array (SGA) Electronic Packages

2003 ◽  
Vol 125 (1) ◽  
pp. 18-23 ◽  
Author(s):  
Michael C. Larson ◽  
Melody A. Verges
Keyword(s):  
Fatigue Crack ◽  
Fatigue Life ◽  
Crack Opening ◽  
Shear Loading ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Force Mode ◽  
Wiring Board ◽  
Crack Growth Model

A fracture mechanics approach is used to investigate how the fatigue life of a solder grid array (SGA) may be increased or decreased by the application of an axial force to individual solder interconnects, such as may be induced by use of an underfill, by warping of a printed wiring board, or by some other mechanical constraint. The predominant loading on the SGA is assumed to be the shear resulting from a difference in thermal expansion between the package and the printed wiring board in the presence of cyclic temperature variations. A fatigue crack growth model, akin to the Paris law, is proposed for the cycles to failure of an individual cracked interconnect which undergoes a cyclic mode-II shear loading in conjunction with either a constant crack opening force (mode-I) or a constant crack closing force. For typical SGA packages in use today, the model predicts that forces on the order of only one newton can significantly impede or accelerate the propagation of a fatigue crack.

Three- and Four-Point Bend Testing for Electronic Packages

2003 ◽  
Vol 125 (4) ◽  
pp. 556-561 ◽  
Author(s):  
Santosh Shetty ◽  
Tommi Reinikainen
Keyword(s):  
Bending Test ◽  
Electronic Packages ◽  
Reliability Model ◽  
Test Results ◽  
Printed Wiring Board ◽  
Reliability Models ◽  
Four Point Bending ◽  
Three Point Bend Test ◽  
Point Bend ◽  
Wiring Board

This study demonstrates the application of three-point and four-point bending tests for evaluating the reliability of chip scale packages under curvature loads. A three-point bend test is conducted on 0.5-mm-pitch chip-scale packages (CSPs) mounted on FR4 (Flame Retardant) substrates. This test is simulated by using the finite element method and the results are calibrated experimentally to formulate a reliability model. A three-point bend scheme is an ideal choice for generating reliability models because multiple packages can be tested under multiple loads in a single test. This reliability model can be used to predict the durability of the packages in the real product under any printed wiring board (PWB) curvature loading conditions. A four-point bending simulation is also demonstrated on the test substrate. Four-point bending test is an ideal method for testing a larger sample size of packages under a particular predefined stress level. This paper describes the bending simulation and testing on packages in a generic sense. Due to the confidentiality of the test results, the package constructional details, material properties, and the actual test data have not been presented here.

Comparison of Warpage Measurement Capabilities and Results Obtained by Using Laser and Digital Fringe Projection Methods

2014 ◽  
Vol 136 (3) ◽  
Author(s):  
Sungbum Kang ◽  
I. Charles Ume
Keyword(s):  
Projection Methods ◽  
Fringe Projection ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Full Field ◽  
Digital Fringe Projection ◽  
Accuracy And Precision ◽  
Wiring Board ◽  
Thermomechanical Reliability ◽  
Measurement Capabilities

Electronic packaged devices are becoming increasingly smaller in size and higher in density while requiring higher performance and superior reliability. Warpage is one of the crucial factors for the thermomechanical reliability of electronic packages and warpage control becomes a more crucial process during the printed wiring board (PWB) fabrication and package assembly processes. This requirement necessitates more accurate methods of measuring warpage. The fringe projection methods are recent trends for measuring the warpage of chip packages, PWBs, and PWB assemblies (PWBAs) because of their noncontact, full-field, and high-resolution measurement capabilities. This paper presents a comparison of two fringe projection methods: laser fringe projection (LFP) (projection moiré) and digital fringe projection (DFP). Experimental results show that digital fringe projection has higher practical resolution, and better accuracy and precision than laser fringe projection.

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