Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2004 ◽  
Vol 126 (3) ◽  
pp. 359-366 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Aging Process ◽  
Flip Chip ◽  
Initial Period ◽  
Bulk Solder ◽  
The Body ◽  
Nano Indentation ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine pitch flip chip assembly processes. The solder bumps and joints that were aged at either 80 °C or 150 °C for up to 440 hours (∼18 days); have been studied by an analysis using micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼50 hours) as compared to the non-aged bumps, but a decrease after longer aging (e.g. 440 hours). A brittle Ag3Sn phase formed as large stick-like features in the body of bulk solder and near the interface of solder/UBM during the initial aging, and is attributed with the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the body of solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a large lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process at 150 °C. These are believed to be detrimental to joint reliability.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2003 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Initial Period ◽  
Electroless Nickel ◽  
Circuit Board ◽  
Solder Paste ◽  
Soldering Process ◽  
Joint Reliability ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine feature flip chip fabrication and assembly processes. The bumps used for characterization were produced by stencil deposition of solder paste onto an electroless Nickel UBM, followed by a bump-forming reflow soldering process and the final assembly joints were then achieved by a subsequent reflow of die onto a fine feature Printed Circuit Board (PCB). The bumps and joints were aged at either 80°C or 150°C for up to 1.5 months and then analyzed by means of micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼ 50h) as compared to as-manufactured bumps, but a decrease after longer aging (e.g. 440 h). A brittle Ag3Sn phase formed as large lamellae in the solder and along the interface between the Cu on the PCB during the initial aging, and is attributed to the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process. These are believed to be detrimental to joint reliability.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

The Study on The Under Bump Metallurgy (Ubm) and 63SN-37PB Solder Bumps Interface for Flip Chip Interconnection

1998 ◽  
Vol 515 ◽  
Author(s):  
Se-Young Jang ◽  
Kyung-Wook Paik
Keyword(s):  
Shear Strength ◽  
Direct Contact ◽  
Flip Chip ◽  
Organic Substrates ◽  
Adhesion Properties ◽  
Ball Shear ◽  
Solder Bumps ◽  
Diffusion Barrier Layer ◽  
Solder Reflow ◽  
Ball Shear Strength

ABSTRACTIn the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

2007 ◽  
Vol 10 (4-5) ◽  
pp. 133-142 ◽  
Author(s):  
Jung-Tang Huang ◽  
Pen-Shan Chao ◽  
Hou-Jun Hsu ◽  
Sheng-Hsiung Shih
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Fine Pitch ◽  
Solder Bumps

A Model for Deformation of Solder Bumps From Ramp Loading

1996 ◽  
Vol 118 (1) ◽  
pp. 37-40
Author(s):  
Lewis S. Goldmann
Keyword(s):  
Experimental Data ◽  
Simple Model ◽  
Solder Joint ◽  
Flip Chip ◽  
Simple Algorithm ◽  
Ball Grid Array ◽  
Joint Reliability ◽  
Subsequent Processing ◽  
Solder Bumps

A simple model is presented to predict the mechanical squashing or stretching of an axisymmetric solder joint when subjected to a ramp loading. This is a situation which can frequently arise, accidentally or by design, in the processing of flip chip solder bumps, or in surface mounted Ball Grid Array modules. Excessive squashing can have ramifications for subsequent processing or for joint reliability. The proposed method, while involving an extremely simple algorithm, has been found to agree well with experimental data, and is very general in its applicability.

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