Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

2004 ◽  
Vol 126 (4) ◽  
pp. 541-545 ◽  
Author(s):  
Y. C. Chan ◽  
M. O. Alam ◽  
K. C. Hung ◽  
H. Lu ◽  
C. Bailey
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Joints ◽  
High Volume ◽  
Fatigue Lifetime ◽  
Solder Interconnection ◽  
Thermal Fatigue Life ◽  
Solder Bumps ◽  
First Time ◽  
Good Agreement

The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fatigue lifetime of the samples since most of the first solder joint failure in the no-flow flip chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment. Our modeling results show good agreement with the experiment that shows underfill entrapment can actually increase the fatigue lifetime of the no-flow flip chip package.

Correlation Between Chemical Reaction and Brittle Fracture Found in Electroless Ni(P)/immersion gold–solder Interconnection

2005 ◽  
Vol 20 (8) ◽  
pp. 1931-1934 ◽  
Author(s):  
Yoon-Chul Sohn ◽  
Jin Yu
Keyword(s):  
Intermetallic Compound ◽  
Brittle Fracture ◽  
Solder Joint ◽  
Chemical Reaction ◽  
Solder Joints ◽  
Interfacial Fracture ◽  
Solder Interconnection ◽  
Failure Locus ◽  
Electroless Ni ◽  
First Time

Occurrence of brittle interfacial fracture at an electroless Ni(P)/immersion gold–solder joint has long been a serious problem not yet fully understood. In our previous report on the electroless Ni(P) [J. Mater. Res.19,2428 (2004)], it was shown that crystallization of the Ni(P) film and growth of the Ni3SnP layer were accelerated after the intermetallic compound (IMC) spalling, and accurate failure locus of the brittle fracture due to so-called “IMC spalling induced microstructure degradation of the Ni(P) film” is presented for the first time in this communication. For Sn–3.0Ag–0.5Cu solder joints, (Ni,Cu)3Sn4and/or (Cu,Ni)6Sn5ternary IMCs formed at the interface, and neither spalling nor interfacial fracture was observed. For Sn–3.5Ag joints, Ni3Sn4compound formed, and the brittle fracture occurred through the Ni3SnP layer in the solder pads where Ni3Sn4had spalled. Since the Ni3SnP layer is getting thicker during or after Ni3Sn4spalling, control of IMC spalling is crucial to ensure the reliability of Ni(P)/solder system.

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Failure Mechanism of Electromigration in Solder Joint

2008 ◽  
Vol 44-46 ◽  
pp. 905-910 ◽  
Author(s):  
Yu Dong Lu ◽  
Xiao Qi He ◽  
Yun Fei En ◽  
Xin Wang
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Joints ◽  
High Current Density ◽  
Electron Flow ◽  
Design Rule ◽  
Bottom Surface ◽  
Constant Density ◽  
Linear Change ◽  
Void Migration

In advanced electronic products, electromigration-induced failure is one of the most serious problems in fine pitch flip chip solder joints because the design rule in devices requires high current density through small solder joints for high performance and miniaturization. The failure mode induced by electromigration in the flip chip solder joint is unique, owing to the loss of under bump metallurgy (UBM) and the interfacial void formation at the cathode contact interface. In this study, Electromigration of flip chip solder joints has been investigated under a constant density of 2.45×104 A/cm2 at 120 °C. The in-situ marker displacements during the electromigration test was measured and found to show a rough linear change as a function of time. Scanning electron microscopic images of the cross section of samples showed the existence of voids at the interface between Al interconnection and under bump metallurgy. The void movement was matched with the marker displacements during the electromigration test, and voids moved to the cathode interface between Al interconnection and under bump metallurgy in the downward electron flow (from chip to substrate) joint. The mechanism of electromigration-induced void migration and failure in the flip chip are discussed. During electromigration, a flux of atoms is driven from the cathode to the anode or a flux of vacancies in the opposite direction. It can lead to two possible mechanisms of void migration. First, if we regard the void as a rigid marker of diffusion, it will be displaced towards the cathode by the atomic flux in the electromigration, Second, if we consider surface diffusion on the void surface, electromigration will drive atoms on the top surface of the void to the bottom surface of the void, and consequently the void will move towards the cathode.

The size effect on intermetallic microstructure evolution of critical solder joints for flip chip assemblies

2015 ◽  
Vol 27 (4) ◽  
pp. 178-184 ◽  
Author(s):  
Ye Tian ◽  
Justin Chow ◽  
Xi Liu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Design Methodology ◽  
Growth Process ◽  
Flip Chip ◽  
Solder Bump ◽  
Solder Joints ◽  
Solder Matrix ◽  
Industrial Practice ◽  
Content Type ◽  
Flip Chips

Purpose – The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix. Design/methodology/approach – This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies. Findings – After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process. Originality/value – With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.

Effect of hourglass shape solder joints on underfill encapsulation process: numerical and experimental studies

2020 ◽  
Vol 32 (3) ◽  
pp. 147-156
Author(s):  
Muhammad Naqib Nashrudin ◽  
Zhong Li Gan ◽  
Aizat Abas ◽  
M.H.H. Ishak ◽  
M. Yusuf Tura Ali
Keyword(s):  
Solder Joint ◽  
Numerical Method ◽  
Flip Chip ◽  
Solder Joints ◽  
Experimental Studies ◽  
Three Dimensional ◽  
Cross Sectional ◽  
Content Type ◽  
Filling Time ◽  
Encapsulation Process

Purpose In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method. Design/methodology/approach Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results. Findings Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints. Practical implications This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages. Originality/value LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

Property of Sn-37Pb solder bumps with different diameter during thermal shock

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Guisheng Gan ◽  
Donghua Yang ◽  
Yi-ping Wu ◽  
Xin Liu ◽  
Pengfei Sun ◽  
...  
Keyword(s):  
Shear Strength ◽  
Solder Joint ◽  
Thermal Shock ◽  
Solder Joints ◽  
Test Method ◽  
Content Type ◽  
Ball Size ◽  
Solder Bumps ◽  
Free Solder ◽  
The Impact

Purpose The impact strength of solder joint under high strain rate was evaluated by board level test method. However, the impact shear test of single solder bump was more convenient and economical than the board level test method. With the miniaturization of solder joints, solder joints were more prone to failure under thermal shock and more attention has been paid to the impact reliability of solder joint. But Pb-free solder joints may be paid too much attention and Sn-Pb solder joints may be ignored. Design/methodology/approach In this study, thermal shock test between −55°C and 125°C was conducted on Sn-37Pb solder bumps in the BGA package to investigate microstructural evolution and growth mechanism of interfacial intermetallic compounds (IMCs) layer. The effects of thermal shock and ball diameter on the mechanical property and fracture behavior of Sn-37Pb solder bumps were discussed. Findings With the increase of ball size, the same change tendency of shear strength with thermal shock cycles. The shear strength of the solder bumps was the highest after reflow; with the increase of the number of thermal shocks, the shear strength of the solder bumps was decreased. But at the time of 2,000 cycles, the shear strength was increased to the initial strength. Minimum shear strength almost took place at 1,500 cycles in all solder bumps. The differences between maximum shear strength and minimum shear strength were 9.11 MPa and 16.83 MPa, 17.07 MPa and 15.59 MPa in φ0.3 mm and φ0.4 mm, φ0.5 mm and φ0.6 mm, respectively, differences were increased with increasing of ball size. With similar reflow profile, the thickness of IMC decreased as the diameter of the ball increased. The thickness of IMC was 2.42 µm and 2.17 µm, 1.63 µm and 1.77 µm with increasing of the ball size, respectively. Originality/value Pb-free solder was gradually used to replace traditional Sn-Pb solder and has been widely used in industry. Nevertheless, some products inevitably used a mixture of Sn-Pb and Pb-free solder to make the transition from Sn-Pb to Pb-free solder. Therefore, it was very important to understand the reliability of Sn-Pb solder joint and more further research works were also needed.

A Model for Deformation of Solder Bumps From Ramp Loading

1996 ◽  
Vol 118 (1) ◽  
pp. 37-40
Author(s):  
Lewis S. Goldmann
Keyword(s):  
Experimental Data ◽  
Simple Model ◽  
Solder Joint ◽  
Flip Chip ◽  
Simple Algorithm ◽  
Ball Grid Array ◽  
Joint Reliability ◽  
Subsequent Processing ◽  
Solder Bumps

A simple model is presented to predict the mechanical squashing or stretching of an axisymmetric solder joint when subjected to a ramp loading. This is a situation which can frequently arise, accidentally or by design, in the processing of flip chip solder bumps, or in surface mounted Ball Grid Array modules. Excessive squashing can have ramifications for subsequent processing or for joint reliability. The proposed method, while involving an extremely simple algorithm, has been found to agree well with experimental data, and is very general in its applicability.

scholarly journals In-situ Study of Electromigration-induced Grain Rotation in Pb-free Solder Joint by Synchrotron Microdiffraction

2008 ◽  
Vol 1116 ◽  
Author(s):  
Kai Chen ◽  
Nobumichi Tamura ◽  
King-Ning Tu
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Solder Joints ◽  
Electric Resistance ◽  
Grain Rotation ◽  
X Ray ◽  
In Situ Study ◽  
Free Solder ◽  
Interconnect Lines

AbstractThe rotation of Sn grains in Pb-free flip chip solder joints hasn't been reported in literature so far although it has been observed in Sn strips. In this letter, we report the detailed study of the grain orientation evolution induced by electromigration by synchrotron based white beam X-ray microdiffraction. It is found that the grains in solder joint rotate more slowly than in Sn strip even under higher current density. On the other hand, based on our estimation, the reorientation of the grains in solder joints also results in the reduction of electric resistivity, similar to the case of Sn strip. We will also discuss the reason why the electric resistance decreases much more in strips than in the Sn-based solders, and the different driving force for the grain growth in solder joint and in thin film interconnect lines.

Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-layered Stacked-chip Packaging

2021 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Shu Kao ◽  
Hou-Chun Liu ◽  
Chia-Ping Hsieh ◽  
Tao-Chih Chang
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Chip Thickness ◽  
Temperature Cycling ◽  
Nonlinear Material ◽  
Element Analysis ◽  
Fatigue Lifetime ◽  
Joint Reliability ◽  
Packaging Structure ◽  
Ic Package

Abstract To overcome the limited operational speed for nano-scaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is the 3D-IC package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of micro solder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg micro solder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg micro solder joint can be achieved at 10 µm of each chip thickness, 230 and 5 µm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermo-mechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

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