Validation of Electronic Package Reliability Using Speckle Interferometry

2002 ◽  
Vol 124 (3) ◽  
pp. 277-280 ◽  
Author(s):  
H.-Y. Yeh ◽  
K. Cote
Keyword(s):  
Thermal Loading ◽  
Printed Circuit Board ◽  
Coefficient Of Thermal Expansion ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Half Cycle ◽  
Electronic Packages ◽  
Snpb Solder ◽  
Shear Strains

In-situ measurements were performed on organic based substrates under mechanical loading as well as land grid array electronic packages under thermal cycling. Whole field displacement measurements obtained from this analysis were compared with results obtained from similar finite element models. The experimental flexibility and results obtained from speckle interferometry indicate that this method has several substantial benefits over moire´ interferometry. Due to coefficient of thermal expansion mismatches between the package and printed circuit board, creep shear strains developed in the 63/37 SnPb solder. When thermally loaded, these creep shear strains develop cracks in the joint leading to Mode II failure. A single thermal half cycle from 25°C to 125°C was applied to a specimen to simulate the fatigue life of the solder joints undergoing thermal loading and the resulting strains were entered into the Engelmaier reliability prediction model for 63/37 SnPb solder. The experimental results yielded 0.59% strain per cycle with 7485 cycles to failure.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Viscoplastic Model Verification for SnPb Solder Based on Creep Tests

2009 ◽  
Author(s):  
Changwoon Han ◽  
Noh-Chang Park ◽  
Chul-Min Oh ◽  
Won-Sik Hong ◽  
Byeongsuk Song
Keyword(s):  
Printed Circuit Board ◽  
Model Verification ◽  
Circuit Board ◽  
Fe Model ◽  
Creep Tests ◽  
Anchor System ◽  
Snpb Solder ◽  
Temperature Load ◽  
Solder Temperature ◽  
Eutectic Snpb

Heat sink assembly for a main board in a server station is built on printed circuit board by an anchor system, mounted by eutectic SnPb solder. Constant high temperature condition in the station keeps solder creeping and makes it failed eventually. To calculate the stress and predict the life of soldered anchor in the station, an FE model of anchor system is built. As viscoplastic behavior of solder depends on several factors such as microstructure of solder, temperature, load, and loading rate, model characteristics should be verified before applying it to life prediction. In this study, Anand unified constitutive equation is adapted for solder modeling and its creep behavior is calibrated and verified based on creep tests.

Packaging Challenges of Thin High Bandwidth POP

2019 ◽  
Author(s):  
Fletcher (Cheng-Piao) Tung ◽  
Jensen (Ying-Chou) Tsai ◽  
Yu-Po Wang ◽  
Joe (Chih-Nan) Lin ◽  
Gary (Yue-Long) Fan
Keyword(s):  
Printed Circuit Board ◽  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Cellular Phone ◽  
Circuit Board ◽  
Printed Circuit ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Application Processor ◽  
Different Thickness

Abstract Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.

scholarly journals Bacterial Concentration Detection using a PCB-based Contactless Conductivity Sensor

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 55 ◽  
Author(s):  
Xiao-Yan Zhang ◽  
Zhe-Yu Li ◽  
Yu Zhang ◽  
Xiao-Qian Zang ◽  
Kosei Ueno ◽  
...  
Keyword(s):  
Flow Cytometry ◽  
Printed Circuit Board ◽  
System Size ◽  
Circuit Board ◽  
Plate Count ◽  
Capacitively Coupled ◽  
Conductivity Sensor ◽  
Relative Standard ◽  
In Situ Detection

Capacitively coupled contactless conductivity detection (C4D) is an improved approach to avoid the problems of labor-intensive, time-consuming and insufficient accuracy of plate count as well as the high-cost apparatus of flow cytometry (FCM) in bacterial counting. This article describes a novel electrode-integrated printed-circuit-board (PCB)-based C4D device, which supports the simple and safe exchange of capillaries and improves the sensitivity and repeatability of the contactless detection. Furthermore, no syringe pump is needed in the detection, it reduces the system size, and, more importantly, avoids the effect on the bacteria due to high pressure. The recovered bacteria after C4D detection at excitation of 25 Vpp and 60–120 kHz were analyzed by flow cytometry, and a survival rate higher than 96% was given. It was verified that C4D detection did not influence the bacterial viability. Moreover, bacteria concentrations from 106 cells/mL to 108 cells/mL were measured in a linear range, and relative standard deviation (RSD) is below 0.2%. In addition, the effects on bacteria and C4D from background solutions were discussed. In contrast to common methods used in most laboratories, this method may provide a simple solution to in situ detection of bacterial cultures.

A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000887-000892 ◽  
Author(s):  
Rudi Hechfellner ◽  
Michiel Kruger ◽  
Tewe Heemstra ◽  
Greg Caswell ◽  
Nathan Blattau ◽  
...  
Keyword(s):  
Solder Joint ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Light Emitting Diodes ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Control ◽  
Circuit Board ◽  
System Level ◽  
Light Emitting ◽  
Printed Circuit

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance. The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime. In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models. It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..

Bare die connections via aerosol jet technology for millimeter wave applications

2019 ◽  
Vol 11 (5-6) ◽  
pp. 441-446
Author(s):  
Franz Xaver Röhrl ◽  
Johannes Jakob ◽  
Werner Bogner ◽  
Robert Weigel ◽  
Stefan Zorn
Keyword(s):  
Printed Circuit Board ◽  
Mechanical Stability ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Circuit Board ◽  
Silver Ink ◽  
Measurement Results ◽  
Bonding Wires ◽  
Technology Transitions ◽  
Rf Performance

AbstractThis paper presents a comparison of chip connections using aerosol jet (AJ) and bond technology on low-cost printed circuit board (PCB) substrates. First, the behavior of the used gap filler material and the used silver ink for AJ technology on PCBs are characterized. In addition to comparing the radio frequency (RF) performance (DC to 67 GHz) of the two technologies, the mechanical stability is also compared. While the AJ technology transitions score above all for their RF performance and the lower requirements (surface finish, pad size, and adhesion) on the PCB, the bonding technology has clear advantages, especially with a different coefficient of thermal expansion values of the substrates to be connected. Finally, the measurement results of a complete package are shown, whereby the chip connection is realized once by means of AJ and once by bonding wires.

scholarly journals Laser-Induced Silver Seeding on Filter Paper for Selective Electroless Copper Plating

Materials ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 1348 ◽  
Author(s):  
Chang-Chun Liu ◽  
Jin Cheng ◽  
Xiao-Qiang Li ◽  
Zhi-Jie Gu ◽  
Kenji Ogino
Keyword(s):  
Composite Film ◽  
Filter Paper ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Silver Particles ◽  
Electroless Copper Plating ◽  
Ag Particles ◽  
Flexible Printed Circuit ◽  
Irradiation Technology

The generation of a flexible printed circuit board on polymer fabrics has been a challenge over the last decade. In this work, a copper pattern was obtained on a soft substrate of filter paper/polyacrylonitrile (FP/PAN) film, where the filter paper was commercially available. The pattern of Ag particles was first produced on an Ag+-doped FP/PAN composite film, followed by electroless plating of copper using the metal silver particles as seeds. The in situ reduction of silver particles and the formation of the silver agglomeration pattern were induced by laser irradiation technology on the FP/PAN/AgNO3 composite film. A variety of characterizations indicated that the resultant copper deposition was uniform, with good conductivity properties.

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