2017 IEEE 35th VLSI Test Symposium (VTS)

VLSI test strategy planning techniques and tools

Computer-Aided Engineering Journal ◽

10.1049/cae.1987.0019 ◽

1987 ◽

Vol 4 (2) ◽

pp. 83 ◽

Cited By ~ 1

Author(s):

K. Baker ◽

R.M. Croft

Keyword(s):

Planning Techniques ◽

Test Strategy ◽

Vlsi Test ◽

Strategy Planning

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Improvement in error resilience for compressed VLSI test data using Hamming code based technique

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2015.7050494 ◽

2015 ◽

Author(s):

Usha Sandeep Mehta ◽

Harikrishna Parmar

Keyword(s):

Test Data ◽

Error Resilience ◽

Hamming Code ◽

Vlsi Test

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The effect of period generation techniques on period resolution and waveform jitter in VLSI test systems

Proceedings International Test Conference 1996. Test and Design Validity ◽

10.1109/test.1996.557126 ◽

2002 ◽

Cited By ~ 2

Author(s):

M.G. Davis

Keyword(s):

Test Systems ◽

Vlsi Test

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VLSI Test technology: Why is the field not sexy enough?

2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) ◽

10.1109/ets.2012.6233047 ◽

2012 ◽

Author(s):

Said Hamdioui ◽

Rob Aitken

Keyword(s):

Vlsi Test ◽

Test Technology

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Teradyne's J967 VLSI Test System: Getting VLSI to the Market on Time

IEEE Design & Test of Computers ◽

10.1109/mdt.1985.294800 ◽

1985 ◽

Vol 2 (6) ◽

pp. 57-62 ◽

Cited By ~ 2

Author(s):

Wayne Ponik

Keyword(s):

Test System ◽

Vlsi Test

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VLSI Test and Hardware Security Background for Hardware Obfuscation

Hardware Protection through Obfuscation ◽

10.1007/978-3-319-49019-9_2 ◽

2017 ◽

pp. 33-68 ◽

Cited By ~ 1

Author(s):

Fareena Saqib ◽

Jim Plusquellic

Keyword(s):

Hardware Security ◽

Vlsi Test

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An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic

Journal of Electronic Testing ◽

10.1007/s10836-020-05880-7 ◽

2020 ◽

Vol 36 (3) ◽

pp. 327-342 ◽

Cited By ~ 1

Author(s):

Sanjoy Mitra ◽

Debaprasad Das

Keyword(s):

Data Compression ◽

Test Data ◽

Ant Colony ◽

Test Data Compression ◽

Compression Scheme ◽

Vlsi Test

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Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 ◽

10.1109/vts.2001.923408 ◽

2001 ◽

Keyword(s):

Vlsi Test

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Evaluation and Analysis of Heuristic Techniques for Vector Ordering of VLSI Test Sets

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2008.917261 ◽

2008 ◽

Vol 57 (9) ◽

pp. 1998-2004 ◽

Cited By ~ 3

Author(s):

H. Hashempour ◽

F. Lombardi

Keyword(s):

Heuristic Techniques ◽

Vlsi Test ◽

Test Sets

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Digital CMOS VLSI test generation: a divide-and-conquer algorithm

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1992.230288 ◽

2003 ◽

Cited By ~ 1

Author(s):

D.-W. Kim ◽

J.H. Schlag ◽

J.L.A. Hughes

Keyword(s):

Test Generation ◽

Divide And Conquer ◽

Digital Cmos ◽

Divide And Conquer Algorithm ◽

Vlsi Test ◽

Cmos Vlsi

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