Efficient Scheduling of Path Delay Tests for Latch-Based Circuits

2009 ◽  
Author(s):  
Kun Young Chung ◽  
Sandeep K. Gupta
Keyword(s):  
Path Delay ◽  
Delay Tests

Analyzing the risk of timing modeling based on path delay tests.

2007 ◽  
Author(s):  
Pouria Bastani ◽  
Benjamin N. Lee ◽  
Li-C. Wang ◽  
Savithri Sundareswaran ◽  
Magdy S. Abadir
Keyword(s):  
Path Delay ◽  
Delay Tests

Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests

2020 ◽  
Vol 37 (4) ◽  
pp. 7-13
Author(s):  
Ankit Shah ◽  
Raman Nayyar ◽  
Arani Sinha
Keyword(s):  
Path Delay ◽  
Delay Tests

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

A new classification of path-delay fault testability in terms of stuck-at faults

2004 ◽  
Vol 19 (6) ◽  
pp. 955-964 ◽  
Author(s):  
Subhashis Majumder ◽  
Bhargab B. Bhattacharya ◽  
Vishwani D. Agrawal ◽  
Michael L. Bushnell
Keyword(s):  
Path Delay ◽  
New Classification ◽  
Delay Fault ◽  
Path Delay Fault
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