Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

26th IEEE VLSI Test Symposium (vts 2008) ◽

10.1109/vts.2008.21 ◽

2008 ◽

Cited By ~ 4

Author(s):

Dongwoo Hong ◽

Kwang-Ting Cheng

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Clock And Data Recovery ◽

Data Recovery ◽

Serial Links ◽

Rate Estimation

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Design for Bit Error Rate estimation of high speed serial links

29th VLSI Test Symposium ◽

10.1109/vts.2011.5783734 ◽

2011 ◽

Cited By ~ 2

Author(s):

Ujjwal Guin ◽

Chen-Huan Chiang

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Serial Links ◽

Rate Estimation

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A 4Gbps clock and data recovery circuit and its bit error rate estimation

2010 IEEE 12th International Conference on Communication Technology ◽

10.1109/icct.2010.5689244 ◽

2010 ◽

Author(s):

Atchit Joshi

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

Clock And Data Recovery ◽

Data Recovery ◽

Rate Estimation

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Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

2006 IEEE International Test Conference ◽

10.1109/test.2006.297723 ◽

2006 ◽

Cited By ~ 1

Author(s):

Dongwoo Hong ◽

Kwang-ting Cheng

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Serial Links ◽

Rate Estimation

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Bit-Error-Rate Estimation for High-Speed Serial Links

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2006.883852 ◽

2006 ◽

Vol 53 (12) ◽

pp. 2616-2627 ◽

Cited By ~ 10

Author(s):

Dongwoo Hong ◽

Chee-Kian Ong ◽

Kwang-Ting Cheng

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Serial Links ◽

Rate Estimation

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Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links

IEEE Solid-State Circuits Magazine ◽

10.1109/mssc.2019.2939342 ◽

2020 ◽

Vol 12 (1) ◽

pp. 25-38

Author(s):

Amir Amirkhany

Keyword(s):

High Speed ◽

Clock And Data Recovery ◽

Data Recovery ◽

Serial Links

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Accurate Bit-Error-Rate estimation for efficient high speed I/O testing

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746334 ◽

2008 ◽

Author(s):

Dongwoo Hong ◽

Kwang-Ting Cheng

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Rate Estimation

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High speed bit error rate estimation in frequency selective time-varying channels

Proceedings of ICCS '94 ◽

10.1109/iccs.1994.474143 ◽

2002 ◽

Author(s):

A.R. Nix ◽

J.P. McGeehan

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

High Speed ◽

Time Varying ◽

Rate Estimation ◽

Frequency Selective ◽

Time Varying Channels

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Tutorial T1C: High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery (CDR)

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid.2018.19 ◽

2018 ◽

Keyword(s):

High Speed ◽

Clock And Data Recovery ◽

Data Recovery ◽

Serial Links

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Efficient Bit Error Rate Estimation for High-Speed Link by Bayesian Model Fusion

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0025 ◽

2015 ◽

Cited By ~ 4

Author(s):

Chenlei Fang ◽

Qicheng Huang ◽

Fan Yang ◽

Xuan Zeng ◽

Xin Li ◽

...

Keyword(s):

Bit Error Rate ◽

Error Rate ◽

Bayesian Model ◽

High Speed ◽

Model Fusion ◽

Rate Estimation

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Design of high-speed burst mode clock and data recovery IC for passive optical network

10.1117/12.628728 ◽

2005 ◽

Author(s):

Minhui Yan ◽

Xiaobin Hong ◽

Wei-Ping Huang ◽

Jin Hong

Keyword(s):

High Speed ◽

Optical Network ◽

Clock And Data Recovery ◽

Data Recovery ◽

Passive Optical Network ◽

Burst Mode

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