Physical design for testability for bridges in CMOS circuits

2002 ◽  
Author(s):  
F.J. Ferguson
Keyword(s):  
Design For Testability ◽  
Physical Design ◽  
Cmos Circuits

scholarly journals Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults

VLSI Design ◽  
1998 ◽  
Vol 5 (4) ◽  
pp. 357-372 ◽  
Author(s):  
Yeong-Ruey Shieh ◽  
Cheng-Wen Wu
Keyword(s):  
Design For Testability ◽  
Cmos Circuits ◽  
Method Performance ◽  
Performance Penalty

We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.

A technique to eliminate glitch power consumption at physical design stage in CMOS circuits

2011 ◽  
Author(s):  
B.V.P. Vasantha Kumar ◽  
N. S. Murthy Sharma ◽  
K. Lal Kishore ◽  
M. Vivekanand ◽  
K. Murthy Raju ◽  
...  
Keyword(s):  
Power Consumption ◽  
Physical Design ◽  
Design Stage ◽  
Cmos Circuits

scholarly journals Physical design challenges to nano-CMOS circuits

2009 ◽  
Vol 6 (11) ◽  
pp. 703-720 ◽  
Author(s):  
Kazuya Masu ◽  
Noboru Ishihara ◽  
Noriaki Nakayama ◽  
Takashi Sato ◽  
Shuhei Amakawa
Keyword(s):  
Physical Design ◽  
Cmos Circuits ◽  
Design Challenges

My-box representation for faulty CMOS circuits

1990 ◽  
Vol 137 (3) ◽  
pp. 225 ◽  
Author(s):  
J.-E. Chen ◽  
C.L. Lee ◽  
W.-Z. Shen
Keyword(s):  
Cmos Circuits

Physical Design, Preparation and Functionalization of Carbon Membranes for Gas Separation

2010 ◽  
Vol 25 (5) ◽  
pp. 449-456 ◽  
Author(s):  
Lin LI ◽  
Tong-Hua WANG ◽  
Yi-Ming CAO ◽  
Jie-Shan QIU
Keyword(s):  
Gas Separation ◽  
Physical Design ◽  
Carbon Membranes
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