DRAM scaling-down to 0.1 μm generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug
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2009 ◽
Vol 44
(1)
◽
pp. 280-284
◽
2003 ◽
Vol 380
(5-6)
◽
pp. 583-588
◽
Keyword(s):