Design of a compact direct digital frequency synthesizer with 12 bit amplitude and 32 bit frequency resolution

2002 ◽  
Author(s):  
G. Fischer ◽  
N.K. Modadugu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Direct Digital Frequency Synthesizer

scholarly journals Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Salah Hasan Ibrahim ◽  
Sawal Hamid Md. Ali ◽  
Md. Shabiul Islam
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Logic Gates ◽  
Sine Wave ◽  
Lookup Table ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Quarter Wave ◽  
Direct Digital Frequency Synthesizer ◽  
Gated Clock

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

Design of a High-Frequency Very Low-Power Direct Digital Frequency Synthesizer

2016 ◽  
Vol 25 (08) ◽  
pp. 1650085 ◽  
Author(s):  
Mojtaba Hasannezhad ◽  
Abumoslem Jannesari ◽  
Mojtaba Lotfizad
Keyword(s):  
Low Power ◽  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Design Method ◽  
Cmos Technology ◽  
Frequency Resolution ◽  
Digital Frequency ◽  
Spurious Free Dynamic Range ◽  
Frequency Independent ◽  
Direct Digital Frequency Synthesizer

This paper presented a low-power Direct Digital Frequency Synthesizer (DDFS) using non-uniform sine-weighted digital-to-analog convertor (DAC). To avoid the need for a sharp filter to generate signals near and beyond the Nyquist frequency, parallel DACs, which cause to speed relaxation in a single DAC as well, and return-to-zero (RZ) technique were used. To reduce the area and power in parallel DACs, non-uniform sine-weighted DAC design method was proposed. This technique causes to reduce power consumption in DACs up to 48.47%, and nearly the same amount of reduction in the area. Meanwhile, by modifying weights of DAC cells, Gilbert cell, the latter block in DDFS structure, was omitted. Although these proposed methods are quite frequency independent, simulations with MATLAB and Cadence in 0.18[Formula: see text][Formula: see text]m CMOS technology were used to demonstrate those. Then, the designed DDFS with 5-bit frequency resolution could generate different output sine signals with acceptable spurious free dynamic range (SFDR).

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