Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) ◽

10.1109/vlsid.2007.76 ◽

2007 ◽

Cited By ~ 3

Author(s):

Sandeep Jain ◽

Jais Abraham ◽

Srinivas Vooka ◽

Sumant Kale ◽

Amit Dutta ◽

...

Keyword(s):

Deterministic Bist

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Weighted Pseudorandom Based Deterministic Bist for Fault Testing and Self-Healing

2019 International Conference on Communication and Electronics Systems (ICCES) ◽

10.1109/icces45898.2019.9002599 ◽

2019 ◽

Cited By ~ 2

Author(s):

G. Bhavani ◽

K. Jamal ◽

B. Veera Reddy

Keyword(s):

Self Healing ◽

Fault Testing ◽

Deterministic Bist

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Two-dimensional test data compression for scan-based deterministic BIST

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966712 ◽

2002 ◽

Cited By ~ 50

Author(s):

Hua-Guo Liang ◽

S. Hellebrand ◽

H.-J. Wunderlich

Keyword(s):

Data Compression ◽

Test Data ◽

Two Dimensional ◽

Test Data Compression ◽

Deterministic Bist

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Deterministic BIST for RNS adders

IEEE Transactions on Computers ◽

10.1109/tc.2003.1214338 ◽

2003 ◽

Vol 52 (7) ◽

pp. 896-906 ◽

Cited By ~ 3

Author(s):

H.T. Vergos ◽

D. Nikolos ◽

M. Bellos ◽

C. Efstathiou

Keyword(s):

Deterministic Bist

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An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Journal of Electronic Testing ◽

10.1007/s10836-008-5077-z ◽

2008 ◽

Vol 24 (6) ◽

pp. 591-595 ◽

Cited By ~ 1

Author(s):

Myung-Hoon Yang ◽

Yongjoon Kim ◽

Sunghoon Chun ◽

Sungho Kang

Keyword(s):

Power Reduction ◽

Effective Power ◽

Deterministic Bist

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Accumulator based deterministic BIST

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743181 ◽

2002 ◽

Cited By ~ 47

Author(s):

R. Dorsch ◽

H.-J. Wunderlich

Keyword(s):

Deterministic Bist

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Pattern generation for a deterministic BIST scheme

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.479997 ◽

2002 ◽

Cited By ~ 82

Author(s):

S. Hellebrand ◽

B. Reeb ◽

S. Tarnick ◽

H.-J. Wunderlich

Keyword(s):

Pattern Generation ◽

Deterministic Bist

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A deterministic BIST scheme based on EDT-compressed test patterns

2015 IEEE International Test Conference (ITC) ◽

10.1109/test.2015.7342398 ◽

2015 ◽

Cited By ~ 1

Author(s):

Grzegorz Mrugalski ◽

Janusz Rajski ◽

Lukasz Rybak ◽

Jedrzej Solecki ◽

Jerzy Tyszer

Keyword(s):

Deterministic Bist

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RTL test pattern generation for high quality loosely deterministic BIST

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253734 ◽

2003 ◽

Cited By ~ 5

Author(s):

M.B. Santos ◽

J.M. Fernandes ◽

I.C. Teixeira ◽

J.P. Teixeira

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

High Quality ◽

Deterministic Bist

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Test Set Embedding for Deterministic BIST Using a Reconfigurable Interconnection Network

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.831593 ◽

2004 ◽

Vol 23 (9) ◽

pp. 1289-1305 ◽

Cited By ~ 45

Author(s):

L. Li ◽

K. Chakrabarty

Keyword(s):

Interconnection Network ◽

Test Set ◽

Deterministic Bist

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Deterministic BIST with multiple scan chains

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743304 ◽

2002 ◽

Cited By ~ 31

Author(s):

G. Kiefer ◽

H.-J. Wunderlich

Keyword(s):

Deterministic Bist ◽

Multiple Scan ◽

Scan Chains

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