Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) ◽

10.1109/vlsid.2007.130 ◽

2007 ◽

Cited By ~ 4

Author(s):

Maryam Ashouei ◽

Muhammad Nisar ◽

Abhijit Chatterjee ◽

Adit Singh ◽

Abdulkadir Diril

Keyword(s):

Cmos Circuits ◽

Nanoscale Cmos ◽

Self Adaptation ◽

Yield Maximization

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An approach based on neural computation to simulate the nanoscale CMOS circuits: Application to the simulation of CMOS inverter

Solid-State Electronics ◽

10.1016/j.sse.2006.12.004 ◽

2007 ◽

Vol 51 (1) ◽

pp. 48-56 ◽

Cited By ~ 46

Author(s):

F. Djeffal ◽

M. Chahdi ◽

A. Benhaya ◽

M.L. Hafiane

Keyword(s):

Neural Computation ◽

Cmos Circuits ◽

Cmos Inverter ◽

Nanoscale Cmos

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Building temperature-insensitive nanoscale CMOS circuits with adaptive voltage power supplies

2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE) ◽

10.1109/ccece.2017.7946786 ◽

2017 ◽

Author(s):

Ming Zhu ◽

Yingtao Jiang ◽

Mei Yang ◽

Xiaohang Wang

Keyword(s):

Power Supplies ◽

Cmos Circuits ◽

Nanoscale Cmos

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PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Microelectronics Reliability ◽

10.1016/j.microrel.2013.09.018 ◽

2014 ◽

Vol 54 (1) ◽

pp. 90-99 ◽

Cited By ~ 19

Author(s):

Vijay Kumar Sharma ◽

Manisha Pattanaik ◽

Balwinder Raj

Keyword(s):

Cmos Circuits ◽

Nanoscale Cmos ◽

Low Leakage ◽

Pvt Variations

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A timing optimization technique for nanoscale CMOS circuits susceptible to process variations

2011 IEEE International Instrumentation and Measurement Technology Conference ◽

10.1109/imtc.2011.5944328 ◽

2011 ◽

Author(s):

Kumar Yelamarthi ◽

Chien-In Henry Chen

Keyword(s):

Optimization Technique ◽

Process Variations ◽

Cmos Circuits ◽

Timing Optimization ◽

Nanoscale Cmos

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Towards Temperature Insensitive Nanoscale CMOS Circuits with Adaptively Regulated Voltage Power Supplies

SSRN Electronic Journal ◽

10.2139/ssrn.3389126 ◽

2017 ◽

Author(s):

Ming Zhu ◽

Yingtao Jiang ◽

Mei Yang ◽

Xiaohang Wang

Keyword(s):

Power Supplies ◽

Cmos Circuits ◽

Nanoscale Cmos

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Analysis of Electromigration in Nanoscale CMOS Circuits

Journal of the Korea Industrial Information Systems Research ◽

10.9723/jksiis.2013.18.1.019 ◽

2013 ◽

Vol 18 (1) ◽

pp. 19-24 ◽

Cited By ~ 1

Author(s):

Kyung Ki Kim

Keyword(s):

Cmos Circuits ◽

Nanoscale Cmos

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Low-leakage techniques for nanoscale CMOS circuits

Nano-CMOS and Post-CMOS Electronics: Circuits and Design ◽

10.1049/pbcs030e_ch5 ◽

2016 ◽

pp. 141-171

Author(s):

Pattanaik ◽

Sharma

Keyword(s):

Cmos Circuits ◽

Nanoscale Cmos ◽

Low Leakage

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A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

International Journal of Electronics ◽

10.1080/00207217.2014.996786 ◽

2015 ◽

Vol 102 (11) ◽

pp. 1852-1866 ◽

Cited By ~ 5

Author(s):

Vijay Kumar Sharma ◽

Manisha Pattanaik

Keyword(s):

Noise Reduction ◽

Reduction Technique ◽

Cmos Circuits ◽

Nanoscale Cmos ◽

Ground Bounce ◽

Noise Reduction Technique

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Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Frontiers of Optoelectronics ◽

10.1007/s12200-013-0328-8 ◽

2013 ◽

Vol 6 (3) ◽

pp. 327-337

Author(s):

Bipin Kumar Verma ◽

Shyam Babu Singh ◽

Shyam Akashe

Keyword(s):

Noise Reduction ◽

Cmos Circuits ◽

Nanoscale Cmos ◽

Ground Bounce

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Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits

2011 International SoC Design Conference ◽

10.1109/isocc.2011.6138626 ◽

2011 ◽

Cited By ~ 3

Author(s):

Ho Joon Lee ◽

Kyung Ki Kim

Keyword(s):

Dielectric Breakdown ◽

Time Dependent ◽

Cmos Circuits ◽

Nanoscale Cmos ◽

Time Dependent Dielectric Breakdown

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