Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks

2011 ◽  
Author(s):  
Hailong Jiao ◽  
Volkan Kursun
Keyword(s):  
Sleep Mode ◽  
Low Leakage

scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

Low-Leakage and Compact Registers with Easy-Sleep Mode

2010 ◽  
Vol 6 (2) ◽  
pp. 263-279 ◽  
Author(s):  
Hailong Jiao ◽  
Volkan Kursun
Keyword(s):  
Sleep Mode ◽  
Low Leakage

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

Integration ◽  
2016 ◽  
Vol 53 ◽  
pp. 68-79 ◽  
Author(s):  
Hailong Jiao ◽  
Yongmin Qiu ◽  
Volkan Kursun
Keyword(s):  
Sleep Mode ◽  
High Data ◽  
Low Leakage

scholarly journals A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

2005 ◽  
Vol 3 ◽  
pp. 355-358
Author(s):  
A. Schmitz ◽  
R. Tielert
Keyword(s):  
Supply Voltage ◽  
Logic Gate ◽  
Deep Submicron ◽  
Soft Error ◽  
Sleep Mode ◽  
Leakage Currents ◽  
Low Leakage ◽  
Sram Cell ◽  
Local Supply ◽  
Standby Mode

Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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