Study and reduction of variability in 28 nm FDSOI technology

2015 ◽  
Author(s):  
Gilles Jacquemod ◽  
Zhaopeng Wei ◽  
Jad Modad ◽  
Yves Leduc ◽  
Philippe Lorenzini ◽  
...  
Keyword(s):  
28 Nm

Combining Current Imaging, EBIC/EBAC, and Electrical Probing for Fast and Reliable In-Situ Electrical Fault Isolation

2016 ◽  
Author(s):  
Stephan Kleindiek ◽  
Matthias Kemmler ◽  
Andreas Rummel ◽  
Klaus Schock
Keyword(s):  
Imaging Technique ◽  
Fault Isolation ◽  
28 Nm

Abstract Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28 nm samples inside an SEM. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults.

High Speed 1-tap Decision Feedback Equalizer in 28 nm CMOS

2014 ◽  
Vol 9 (9th) ◽  
pp. 1-12
Author(s):  
Mostafa Hosny ◽  
Sameh Ibrahim ◽  
DiaaEldin Khalil ◽  
Mohamed Dessouky
Keyword(s):  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
28 Nm

A Simultaneous Phase Shifter and Up-Converter for the 28/38/60-GHz Bands in 28-nm CMOS

2020 ◽  
Author(s):  
David del Rio ◽  
Chia-Jen Liang ◽  
Ching-Wen Chiang ◽  
Roc Berenguer ◽  
Mau-Chung Frank Chang ◽  
...  
Keyword(s):  
Phase Shifter ◽  
60 Ghz ◽  
28 Nm

Gate Leakage for 28 nm Stacked HfZrOx Dielectric of p-Channel MOSFETs After Decoupled Plasma Nitridation Treatment With Annealing Temperatures

2014 ◽  
Vol 42 (12) ◽  
pp. 3712-3715 ◽  
Author(s):  
Shea-Jue Wang ◽  
Mu-Chun Wang ◽  
Win-Der Lee ◽  
Jie-Min Yang ◽  
L. S. Huang ◽  
...  
Keyword(s):  
Gate Leakage ◽  
Plasma Nitridation ◽  
Annealing Temperatures ◽  
28 Nm

Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor

2021 ◽  
Author(s):  
Shuting Shi ◽  
Rui Chen ◽  
Rui Liu ◽  
Mo Chen ◽  
Chen Shen ◽  
...  
Keyword(s):  
Single Event Upset ◽  
Single Event ◽  
Arm Processor ◽  
28 Nm

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

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