A Concurrent Built-In Self-Test Architecture Based on a Self-Testing RAM

2005 ◽  
Vol 54 (1) ◽  
pp. 69-78 ◽  
Author(s):  
I. Voyiatzis ◽  
A. Paschalis ◽  
D. Gizopoulos ◽  
N. Kranitis ◽  
C. Halatsis
Keyword(s):  
Self Testing ◽  
Self Test ◽  
Built In Self Test ◽  
Test Architecture

scholarly journals Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

VLSI Design ◽  
1998 ◽  
Vol 7 (2) ◽  
pp. 191-201
Author(s):  
Sunil R. Das ◽  
Nita Goel ◽  
Wen B. Jone ◽  
Amiya R. Nayak
Keyword(s):  
Fault Detection ◽  
Vlsi Circuits ◽  
Internal Line ◽  
Single Output ◽  
Signature Generation ◽  
Self Testing ◽  
Vlsi Technology ◽  
Self Test ◽  
Built In Self Test

In this paper, we focus on the use of signature-based output compaction technique for built-in self-testing of VLSI circuits. We give algorithm for single-output and multiple-output signature generation using exhaustive test patterns extending the syndrome conccpt. The signature wc develop is a functional signature and is very effective for both input and internal line fault detection, as seen from simulation on various benchmark circuits. The signature generators can bc easily implemented using the current VLSI technology.

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC

2021 ◽  
Author(s):  
Donghyun Han ◽  
Youngkwang Lee ◽  
Sooryeong Lee ◽  
Sungho Kang
Keyword(s):  
3D Ic ◽  
Self Test ◽  
Built In Self Test ◽  
Test Architecture

Arithmetic module-based built-in self test architecture for two-pattern testing

2012 ◽  
Vol 6 (4) ◽  
pp. 195
Author(s):  
I. Voyiatzis ◽  
C. Efstathiou ◽  
H. Antonopoulou ◽  
A. Milidonis
Keyword(s):  
Self Test ◽  
Built In Self Test ◽  
Test Architecture
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