A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test

2020 ◽  
Vol 69 (6) ◽  
pp. 3516-3526 ◽  
Author(s):  
Tao Chen ◽  
Chulhyun Park ◽  
Hao Meng ◽  
Dadian Zhou ◽  
Jose Silva-Martinez ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Solution ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
Linearity Test

A Mixed-Voltage Sensor Readout Circuit With On-Chip Calibration and Built-In Self-Test

2007 ◽  
Vol 7 (9) ◽  
pp. 1225-1232 ◽  
Author(s):  
Andrew Mason ◽  
Abhijeet V. Chavan ◽  
Kensall D. Wise
Keyword(s):  
Voltage Sensor ◽  
Readout Circuit ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip

scholarly journals BIST Architecture for Magnetic Memories

2020 ◽  
pp. 88-95
Author(s):  
Armen Babayan
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Test Solution ◽  
Access Memory ◽  
Magnetic Random Access Memory ◽  
Emerging Memory ◽  
Self Test ◽  
Built In Self Test

Magnetic random-access memory (MRAM) is one of the emerging memory technologies, which can be considered as the next universal memory because of its good parameters. Nevertheless, this type of memory is not guaranteed from defects and it is very important to understand the fault typology and develop a test solution that addresses these faults. In this paper a Built-in Self-Test (BIST) solution is presented, which is specifically tailored for MRAMs and efficiently deals with MRAM specific faults.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

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