A circular pipeline processing based deterministic parallel test pattern generator

2013 ◽  
Author(s):  
Kuen-Wei Yeh ◽  
Jiun-Lang Huang ◽  
Hao-Jan Chao ◽  
Laung-Terng Wang
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Parallel Test ◽  
Pipeline Processing

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator

2016 ◽  
Vol 32 (5) ◽  
pp. 625-638 ◽  
Author(s):  
Kuen-Wei Yeh ◽  
Jiun-Lang Huang ◽  
Laung-Terng Wang
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Parallel Test ◽  
Pipeline Processing

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

2015 ◽  
Author(s):  
Chun-Hao Chang ◽  
Kuen-Wei Yeh ◽  
Jiun-Lang Huang ◽  
Laung-Terng Wang
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Zero Inflation ◽  
Parallel Test

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

scholarly journals UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

Integration ◽  
2016 ◽  
Vol 55 ◽  
pp. 85-97 ◽  
Author(s):  
Cinzia Bernardeschi ◽  
Luca Cassano ◽  
Andrea Domenici ◽  
Luca Sterpone
Keyword(s):  
Test Pattern ◽  
Pattern Generator
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