Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing

2011 IEEE International Test Conference ◽

10.1109/test.2011.6139132 ◽

2011 ◽

Cited By ~ 3

Author(s):

Yi-Tsung Lin ◽

Jiun-Lang Huang ◽

Xiaoqing Wen

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Clock Gating ◽

Scan Testing

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PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

2008 17th Asian Test Symposium ◽

10.1109/ats.2008.63 ◽

2008 ◽

Cited By ~ 4

Author(s):

Yi-Tsung Lin ◽

Meng-Fan Wu ◽

Jiun-Lang Huang

Keyword(s):

Power Supply ◽

Test Pattern ◽

Pattern Generation ◽

Huffman Coding ◽

Test Pattern Generation ◽

Scan Testing ◽

Test Compression ◽

Generation Technique ◽

Supply Noise ◽

Noise Test

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Test pattern generation for logic crosstalk faults in VLSI circuits

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1991.0034 ◽

1991 ◽

Vol 138 (2) ◽

pp. 179 ◽

Cited By ~ 3

Author(s):

A. Rubio ◽

J.A. Sainz ◽

K. Kinoshita

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Vlsi Circuits ◽

Test Pattern Generation

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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Machine Intelligence for Efficient Test Pattern Generation

2020 IEEE International Test Conference (ITC) ◽

10.1109/itc44778.2020.9325250 ◽

2020 ◽

Author(s):

Soham Roy ◽

Spencer K. Millican ◽

Vishwani D. Agrawal

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Machine Intelligence ◽

Test Pattern Generation ◽

Efficient Test

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An automatic test pattern generation framework for combinational threshold logic networks

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347974 ◽

2004 ◽

Cited By ~ 6

Author(s):

P. Gupta ◽

Rui Zhang ◽

N.K. Jha

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Threshold Logic ◽

Automatic Test

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Analysis of optimization algorithms in automated test pattern generation for sequential circuits

2017 IEEE International Conference on Systems, Man, and Cybernetics (SMC) ◽

10.1109/smc.2017.8122883 ◽

2017 ◽

Cited By ~ 1

Author(s):

Majed M. Alateeq ◽

Witold Pedrycz

Keyword(s):

Test Pattern ◽

Optimization Algorithms ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automated Test

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Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

International Journal of High Performance Systems Architecture ◽

10.1504/ijhpsa.2016.076204 ◽

2016 ◽

Vol 6 (1) ◽

pp. 51 ◽

Cited By ~ 3

Author(s):

J.P. Anita ◽

P. Sudheesh

Keyword(s):

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Test Pattern Generation ◽

Decision Diagrams ◽

Test Power ◽

Multiple Faults ◽

Test Power Reduction

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Automatic test pattern generation can be solved as a constraint satisfaction problem

Microprocessing and Microprogramming ◽

10.1016/0165-6074(93)90216-8 ◽

1993 ◽

Vol 38 (1-5) ◽

pp. 715-722

Author(s):

K. Tilly ◽

L. Surján ◽

G. Román

Keyword(s):

Constraint Satisfaction ◽

Test Pattern ◽

Constraint Satisfaction Problem ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Automatic Test

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Cited By ~ 15

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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A comparative analysis of bio-inspired optimization algorithms for automated test pattern generation in sequential circuits

Applied Soft Computing ◽

10.1016/j.asoc.2020.106967 ◽

2021 ◽

Vol 101 ◽

pp. 106967

Author(s):

Majed Alateeq ◽

Witold Pedrycz

Keyword(s):

Comparative Analysis ◽

Test Pattern ◽

Optimization Algorithms ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automated Test

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