Delay fault simulation with bounded gate delay mode

2007 IEEE International Test Conference ◽

10.1109/test.2007.4437637 ◽

2007 ◽

Cited By ~ 6

Author(s):

Soumitra Bose ◽

Hillary Grimes ◽

Vishwani D. Agrawal

Keyword(s):

Fault Simulation ◽

Gate Delay ◽

Delay Fault

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Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) ◽

10.1109/ats.1998.741599 ◽

2002 ◽

Cited By ~ 2

Author(s):

H. Takahashi ◽

K.O. Boateng ◽

Y. Takamatsu

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Gate Delay ◽

Combinational Circuits ◽

Delay Fault

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Path delay fault simulation algorithms for sequential circuits

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224444 ◽

2003 ◽

Cited By ~ 13

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Simulation Algorithms

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Parallel concurrent path-delay fault simulation using single-input change patterns

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489647 ◽

2002 ◽

Cited By ~ 4

Author(s):

M.A. Gharaybeh ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Single Input

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GPU-Accelerated Small Delay Fault Simulation

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0077 ◽

2015 ◽

Cited By ~ 14

Author(s):

Eric Schneider ◽

Stefan Holst ◽

Michael A. Kochte ◽

Xiaoqing Wen ◽

Hans-Joachim Wunderlich

Keyword(s):

Fault Simulation ◽

Delay Fault ◽

Small Delay

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A delay fault model for at-speed fault simulation and test generation

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1145/1233501.1233521 ◽

2006 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Fault Model ◽

Delay Fault

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Accelerated path delay fault simulation

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232715 ◽

2003 ◽

Author(s):

Yuejian Wu ◽

A. Ivanov

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Gate-delay-fault testability properties of multiplexor-based networks

Formal Methods in System Design ◽

10.1007/bf01383945 ◽

1993 ◽

Vol 2 (1) ◽

pp. 93-112 ◽

Cited By ~ 1

Author(s):

Pranav Ashar ◽

Srinivas Devadas ◽

Kurt Keutzer

Keyword(s):

Gate Delay ◽

Delay Fault ◽

Gate Delay Fault

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Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Microprocessors and Microsystems ◽

10.1016/j.micpro.2015.05.003 ◽

2015 ◽

Vol 39 (8) ◽

pp. 1130-1138

Author(s):

Jaak Kõusaar ◽

Raimund Ubar ◽

Sergei Devadze ◽

Jaan Raik

Keyword(s):

Critical Path ◽

Fault Simulation ◽

Delay Fault ◽

Transition Delay

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False-path removal using delay fault simulation

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) ◽

10.1109/ats.1998.741593 ◽

2002 ◽

Cited By ~ 3

Author(s):

M.A. Gharaybeh ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Delay Fault ◽

False Path

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Test generation for multiple-threshold gate-delay fault model

Proceedings 10th Asian Test Symposium ◽

10.1109/ats.2001.990290 ◽

2002 ◽

Cited By ~ 7

Author(s):

M. Nakao ◽

Y. Kiyoshige ◽

K. Hatayama ◽

Y. Sato ◽

T. Nagumo

Keyword(s):

Test Generation ◽

Fault Model ◽

Gate Delay ◽

Delay Fault ◽

Multiple Threshold ◽

Gate Delay Fault ◽

Threshold Gate

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