Global failure localization: we have to, but on what and how?

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

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Analysis of Delta Iddq Soft Fails on Pass Chips

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0305 ◽

2006 ◽

Author(s):

I. Österreicher ◽

S. Eckl ◽

B. Tippelt ◽

S. Döring ◽

R. Prang ◽

...

Keyword(s):

Failure Analysis ◽

Failure Mode ◽

Photon Emission ◽

Complete Analysis ◽

Functional Tests ◽

Analysis Techniques ◽

Atomic Force ◽

Current Consumption ◽

Emission Microscopy ◽

Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

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Failure Localization of Intermittent Short Failures Caused by Vertical Conductive Anodic Filament Formation

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0218 ◽

2014 ◽

Author(s):

Daniel Nuez ◽

Phoumra Tan

Keyword(s):

Glass Fibers ◽

Vertical Plane ◽

Axis Formation ◽

Metal Trace ◽

Conductive Anodic Filament ◽

Plated Through Hole ◽

Voltage Gradients ◽

Ic Package ◽

Through Hole ◽

Failure Localization

Abstract Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.

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Comparison of Active and Passive Voltage Contrast for Failure Localization

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0331 ◽

2007 ◽

Author(s):

R. Rosenkranz ◽

W. Werner

Keyword(s):

Case Studies ◽

Optical Beam ◽

Leakage Currents ◽

Localization Method ◽

Voltage Contrast ◽

Failure Localization

Abstract In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

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SRAM Failure Analysis Strategy

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0177 ◽

2003 ◽

Author(s):

P. Egger ◽

C. Burmer

Keyword(s):

Liquid Crystal ◽

Failure Analysis ◽

The Other ◽

Other Hand ◽

Analysis Strategy ◽

Emission Microscopy ◽

Metal Layers ◽

Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

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Failure Localization in a Multistage S-Band Power Amplifier

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0373 ◽

2016 ◽

Author(s):

Clarence Rebello ◽

Ted Kolasa ◽

Parag Modi

Keyword(s):

Output Power ◽

Power Amplifier ◽

Fault Tree ◽

Root Cause ◽

Failure Investigation ◽

Band Power ◽

Cause Of Failure ◽

Design Materials ◽

Board Level ◽

Failure Localization

Abstract During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

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